Semiconductor memory device
AssigneeNEC Corporation
InventorYuji Muraoka
Life of this patent
Estimating the term…
Abstract
An output circuit for a semiconductor memory device includes at least an output transistor and a level conversion circuit. In this case, the level conversion circuit is connected to the output transistor. The output transistor is connected to a ground terminal and an output terminal. In this condition, the level conversion circuit converts an input signal in level and supplies the converted input signal to the output transistor as drive signal. With such a structure, a predetermined booster voltage is given to the level conversion circuit. Consequently, the ground potential appears at the output terminal without an access delay when the output transistor is turned on by the drive signal.
Claims11
An output circuit for a semiconductor memory device, comprising:
- a first terminal which is given a power supply voltage;
- a second terminal which is given a ground potential;
- first and second transistors which are connected between the first and second terminals;
- a first level conversion circuit which is connected to the first transistor and which converts a first input signal in level and supplies the converted first signal to said first transistor as a first drive signal;
- a second level conversion circuit which is connected to the second transistor and which converts a second input signal in level and supplies the converted second signal to said second transistor as a second drive signal;
- and
- an output terminal which is connected between the first and second transistors;
- a predetermined booster voltage different from the power supply voltage being given to the first and second conversion circuits;
- wherein said first and second input signals include a signal read from one of a plurality of memory cells contained within an array portion of a plurality of memory arrays.
An output circuit for a semiconductor memory device, comprising:
- a ground terminal which is given a ground potential;
- an output transistor which is connected to the ground terminal;
- a level conversion circuit which is connected to the output transistor and which converts an input signal in level and supplies the converted input signal to said output transistor as a drive signal;
- and
- an output terminal which is connected to said output transistor;
- a predetermined booster voltage being given to said level conversion circuit so that the ground potential appears at the output terminal without an access delay when said output transistor is turned on by the drive signal;
- wherein said input signal includes a signal read from one of a plurality of memory cells contained within an array portion of a plurality of memory arrays.
A semiconductor memory device comprising;
- a plurality of memory arrays each of which includes an array portion having a plurality of memory cells and an output circuit which is given a signal read from one of the plurality of memory cells;
- a ground terminal which is given a ground potential;
- a ground line which is connected to the ground terminal;
- a plurality of output transistors each of which is provided in said output circuit and which are connected to said ground terminal via the ground line;
- a plurality of level conversion circuits each of which is arranged in said output circuit and each of which is given a signal read from the memory cell as an input signal, converts the input signal in level and supplies the converted input signal to said transistor as a drive signal.
Dependencies are inferred from the claim text.