Multi-state flash EEPROM system with defect management including an error correction scheme

In an integrated circuit memory system including an array of non-volatile floating gate memory cells wherein individual cells are addressable for programming and reading their states, a method of operating said memory system, comprising:

• providing a plurality of programmed states in excess of two for the individual cells of the array, whereby the cells individually store more than one bit of data,
• providing a plurality of distinct blocks of said memory cells, wherein the cells of the individual blocks are erasable together to a base state from which one or more of the memory cells within an erased block may be subsequently reprogrammed,
• addressing at least one of said plurality of blocks and initiating an erase cycle of the memory cells therein,
• determining the states of the memory cells within said at least one block during the erase cycle,
• terminating the erase cycle either when all of the memory cells of said at least one block are determined to be erased to the base state or when a predefined condition is reached before all of the cells of said at least one block are erased,
• if the erase cycle is terminated before all the cells of said at least one block are erased, determining whether the number of unerased memory cells within said at least one block is less than or greater than a permitted number, said permitted number being substantially the maximum number of cells whose data, if bad, are correctable by an error correction scheme,
• if the number of unerased cells within said at least one block is less than said permitted number, reprogramming memory cells within the erased said at least one block with new data, and
• if the number of unerased cells within said at least one block is greater than said permitted number, substituting other redundant memory cells for the unerased memory cells.

A method of operating a memory system having an array of non-volatile floating gate memory cells formed on an integrated circuit, comprising:

• providing a plurality of programmed states in excess of two for the individual memory cells of the array, whereby the memory cells individually store more than one bit of data,
• providing a plurality of distinct blocks of said memory cells, wherein the memory cells of the individual blocks are erasable together,
• determining whether there are any defective cells within at least one of said plurality of memory cell blocks and, if so, a number of such defective cells,
• comparing the number of defective cells within said at least one block with a maximum predetermined number of cells which, if defective, still permits correction of data stored in said at least one block by use of an error correction scheme, and
• if the number of defective cells within said at least one block is greater than said predetermined number, substituting other redundant memory cells for the defective memory cells.

A method of operating a memory system having an array of non-volatile floating gate memory cells formed on an integrated circuit, comprising:

• providing a plurality of programmed states in excess of two for the individual memory cells of the array, whereby the memory cells individually store more than one bit of data,
• providing a plurality of distinct blocks of said memory cells, wherein the memory cells of the individual blocks are erasable together,
• determining whether there are any defective cells within the array and, if so, a number of such defective cells,
• comparing the number of defective cells within the array with a maximum predetermined number of cells which, if defective, still permits correction of data stored in the array by use of an error correction scheme, and
• if the number of defective cells within the array is greater than said predetermined number, substituting other redundant memory cells for the defective memory cells.