Multi-state flash EEprom system with defect handling

A fault-tolerant memory system, comprising:

• an array of flash EEPROM cells that are individually programmable into more than two states in order to store more than one bit of data per cell;
• a plurality of flash erasable sectors partitioned from said array such that all cells within each sector are erasable together;
• redundant cells within said array for substituting one or more defective cells;
• a memory controller coupled to the array for controlling memory operations of the array;
• error detection means operated with said memory controller during use of the memory for detecting one or more defective cells within a given sector;
• a defect map maintained by said memory controller during use of the memory and stored within the array for storing addresses of said detected one or more defective cells;
• and
• defective cell substituting means for substituting said one or more defective cells within a given sector with a corresponding number of redundant cells.

A system for correcting errors from defective cells within an array of flash EEprom cells that are individually programmable into more than two states in order to store more than one bit of data per cell, comprising:

• a plurality of flash erasable sectors partitioned from said array such that all cells within each sector are erasable together;
• a circuit that programs individual cells within the sectors into one of said more than two states according to data being stored in the array;
• redundant cells within said array for substituting one or more defective cells;
• error detection means for detecting one or more defective cells within a given sector;
• defective cell substituting means for substituting said one or more defective cells within a given sector with a corresponding number of redundant cells;
• and
• wherein said redundant cells are in the same sector as the defective cells when the defective cells in the sector do not exceed a predetermined number, and said redundant cells are in a different sector when said predetermined number is exceeded.

A fault-tolerant memory system for correcting bad data in defective cells within an array of flash EEprom cells that are individually programmable into more than two states in order to store more than one bit of data per cell, comprising:

• a circuit that programs individual cells into one of said more than two states according to data being stored in the array;
• redundant cells within the array for storing good data intended for the defective cells;
• a memory controller coupled to the array for controlling memory operations of the array;
• error detection means operated with said memory controller during use of the memory for detecting a defect and its address within the array;
• a defect map maintained by said memory controller during use of the memory and stored within the array for storing the address of said detected defect;
• and
• data substituting means operated with said memory controller and responsive to said defect map for substituting the bad data in said detected defect with the good data in a corresponding number of redundant cells.

A system for correcting bad data in defective cells within an array of flash EEprom cells that are individually programmable into more than two states in order to store more than one bit of data per cell, comprising:

• a circuit that programs individual cells into one of said more than two states according to data being stored in the array;
• redundant cells within the array, for storing good data intended for the defective cells;
• a memory controller coupled to the array for controlling memory operations of the array;
• error detection means operated with said memory controller for detecting any defective cells within the array;
• a defect map maintained by said memory controller and stored within the array for storing addresses of defective cells;
• data substituting means operated with said memory controller and responsive to said defect map for substituting the bad data in a detected defective cell with the good data in a corresponding redundant cell;
• means for automatically saving the good data intended to be written to the defective cells to the corresponding redundant cells, thereby preserving the integrity of the good data;
• and
• said array being partitioned into a plurality of flash erasable sectors such that all cells within each sector are erasable together.

A system for correcting bad data in defective cells within an array of flash EEprom cells that are individually programmable into more than two states in order to store more than one bit of data per cell, comprising:

• a circuit that programs individual cells into one of said more than two states according to data being stored in the array;
• redundant cells within the array for storing good data intended for the defective cells;
• a memory controller coupled to the array for controlling memory operations of the array;
• error detection means operated with said memory controller for detecting any defective cells within the array;
• a defect map maintained by said memory controller and stored within the array for storing addresses of defective cells;
• data substituting means operated with said memory controller and responsive to said defect map for substituting the bad data in a detected defective cell with the good data in a corresponding redundant cell;
• means for automatically saving the good data intended to be written to the defective cells to the corresponding redundant cells, thereby preserving the integrity of the good data;
• and wherein
• said array is partitioned into a plurality of flash erasable sectors such that all cells within each sector are erasable together, and each sector has redundant cells therein for substituting defective cells that arise in said each sector.

A system for correcting bad data in defective cells within an array of flash EEprom cells that are individually programmable into more than two states in order to store more than one bit of data per cell, comprising:

• a circuit that programs individual cells into one of said more than two states according to data being stored in the array;
• redundant cells within the array for storing good data intended for the defective cells;
• a memory controller coupled to the array for controlling memory operations of the array;
• error detection means operated with said memory controller for detecting any defective cells within the array;
• a defect map maintained by said memory controller and stored within the array for storing addresses of defective cells;
• data substituting means operated with said memory controller and responsive to said defect map for substituting the bad data in a detected defective cell with the good data in a corresponding redundant cell;
• means for automatically saving the good data intended to be written to the defective cells to the corresponding redundant cells, thereby preserving the integrity of the good data;
• and
• said array being partitioned into a plurality of flash erasable sectors such that all cells within each sector are erasable together, wherein the defect map for a defective cell is stored in a sector containing the defective cell.

A system for correcting bad data in defective cells within an array of flash EEprom cells that are individually programmable into more than two states in order to store more than one bit of data per cell, comprising:

• a circuit that programs individual cells into one of said more than two states according to data being stored in the array;
• redundant cells within the array for storing good data intended for the defective cells;
• a memory controller coupled to the array for controlling memory operations of the array;
• error detection means operated with said memory controller for detecting any defective cells within the array;
• a defect map maintained by said memory controller and stored within the array for storing addresses of defective cells;
• data substituting means operated with said memory controller and responsive to said defect map for substituting the bad data in a detected defective cell with the good data in a corresponding redundant cell;
• and
• said array being partitioned into a plurality of flash erasable sectors such that all, cells within each sector are erasable together, wherein said redundant cells are in the same sector as the defective cells when the defective cells in the sector do not exceed a predetermined number, and said redundant cells are in a different sector when said predetermined number is exceeded.

A fault-tolerant memory system, comprising:

• an array of flash EEprom cells that are individually programmable into more than two states in order to store more than one bit of data per cell;
• a memory controller coupled to the array for controlling memory operations of the array;
• error detection means operated with said memory controller during use of the memory for detecting a defect within the array, said detected defect comprising at least one defective cell;
• redundant cells within the array for substituting said at least one defective cell;
• defective cell mapping means operated with said memory controller for mapping said at least one defective cell to a corresponding redundant cell substituting therefor;
• a defect map maintained by said memory controller during use of the memory and stored within the array for storing information related to the mapping of said at least one defective cell to the corresponding redundant cell, such that when said detected defect is being accessed, said memory controller, responsive to said defect map, accesses the corresponding redundant cell.

A method of handling defects within an array of flash EEprom cells that are individually programmable into more than two states in order to store more than one bit of data per cell, comprising the steps of:

• programming the individual cells of the array into one of said more than two programmable states;
• providing a memory controller coupled to the array for controlling memory operations of the array;
• using said memory controller to detect a defect within a the array during use of the memory, said detected defect comprising at least one defective cell;
• providing redundant cells within the array for substituting said at least one defective cell;
• using said memory controller to map said at least one defective cell to a corresponding redundant cell substituting therefor;
• using said memory controller during use of the memory to maintain a defect map and storing said defect map within the array, said defect map storing information related to the mapping of said at least one defective cell to the corresponding redundant cell, such that when said detected defect is being accessed, said memory controller, responsive to said defect map, accesses the corresponding redundant cell.

A fault-tolerant memory system, comprising:

• an array of flash EEPROM cells that are individually programmable into more than two states in order to store more than one bit of data per cell;
• a plurality of flash erasable sectors being partitioned in said array such that all cells within each sector are erasable together;
• a memory controller coupled to the array for controlling memory operations of the array;
• detection means operated with said memory controller during use of the memory for detecting an error condition within a first sector containing data;
• sector mapping means operated with said memory controller in response to said error condition during memory operations for mapping said data in first sector to a corresponding second sector substituting therefor;
• and
• a map maintained by said memory controller during use of the memory and stored within the array for holding information related to the mapping of said data to the corresponding second sector, such that when said data is being accessed, responsive to said map the corresponding second sector is being accessed.

A method of handling defects within an array of flash EEprom cells that are individually programmable into more than two states in order to store more than one bit of data per cell, comprising the steps of:

• partitioning said array into a plurality of flash erasable sectors such that all cells within each sector are erasable together;
• controlling memory operations of the array, the memory operations including normal operations such as erasing, programming and reading of data in the array;
• programming the individual cells of the array into one of said more than two programmable states;
• detecting an error condition within a first sector during a normal operation of the array;
• mapping in response to said error condition said first sector to a corresponding second sector substituting therefor;
• maintaining and storing a map within the array during normal operations for holding information related to the mapping of said first section to the corresponding second sector;
• and
• subsequently causing the second sector to be accessed instead of said first sector whenever said first sector is being accessed.

A method of handling defects within an array of flash EEprom cells that are individually programmable into more than two states in order to store more than one bit of data per cell, comprising the steps of:

• partitioning said array into a plurality of flash erasable sectors such that all cells within each sector are erasable together;
• providing redundant cells within each sector for substituting defective cells;
• coupling a memory controller to the array for controlling memory operations of the array;
• detecting one or more defective cells within a given sector with said memory controller during use of the memory;
• maintaining a defect map of addresses of said detected one or more defective cells during use of the memory;
• storing said defect map within the array;
• and
• substituting said detected one or more defective cells within a given sector with a corresponding number of redundant cells.