Method and device for erasing non-volatile semiconductor memory with smaller erase variation
AssigneeNEC Corporation
InventorToshikatsu Jinbo
Life of this patent
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Abstract
Step S1 is carried out to lower, at the beginning of erasing operation, a voltage across a drain of a memory cell below a positive voltage applied to a source for erasing and then step S2 is carried out to open the drain. At the beginning of the erasing operation, step S3 is carried out to apply the positive voltage to the source and then step S3-1 is carried out to apply a negative voltage to a gate. To complete the erasing operation, step S4 is carried out to force the gate to be at the ground level and then the source to be at the ground level.
Claims15
A method for erasing a non-volatile semiconductor memory in which data are erased from memory cells by means of applying a positive voltage to sources of the individual memory cells while opening drains of the memory cells, wherein said method comprising a first erasing mode successively carrying out:
- a first step for discharging the drains of the memory cells to lower the voltage across the drains of the memory cells below the positive voltage applied to the sources;
- a second step for opening the drains of the memory cells;
- and a third step for applying the positive voltage to the sources of the memory cells;
- and
- a second erasing mode successively carrying out:
- a fourth step for forcing the gates of the memory cells to be at the ground level;
- and a fifth step for forcing the sources of the memory cells to be at the ground level.
A device for erasing a non-volatile semiconductor memory in which data are erased from memory cells by means of applying a positive voltage to sources of the individual memory cells while opening drains of the memory cells, wherein said device comprising:
- first means for discharging the drains of the memory cells to lower the voltage across the drains of the memory cells below the positive voltage applied to the sources and then opening the drains of the memory cells;
- second means for applying the positive voltage to the sources of the memory cells after the drains are opened;
- and
- third means for forcing the gates of the memory cells to be at the ground level during erasing operation;
- said second means forcing the sources of the memory cells to be at the ground level after the gates of the memory cells are forced to be at the ground level by said third means.
Dependencies are inferred from the claim text.