Mixed mode erase method to improve flash eeprom write/erase threshold closure

A non-volatile semiconductor memory device comprising:

• a) a semiconductor substrate of a first conductivity type;
• b) a first diffusion well of a second conductivity type diffused into said semiconductor substrate;
• c) a second diffusion well of the first conductivity type diffused into said first diffusion well
• d) a pair of diffusions of a second conductivity type spaced distally from one another to form a source region and a drain region within said second diffusion well;
• e) a tunneling oxide insulation disposed upon said semiconductor substrate in a region generally between the source region and drain region in correspondence with a channel region and having a thickness which allows tunneling of carriers there through;
• f) a floating gate electrode disposed upon said tunneling oxide insulation generally in correspondence with said channel region;
• g) an inter-poly dielectric insulation disposed upon said floating gate electrode to insulate said floating gate;
• h) a control gate electrode disposed upon said inter-poly dielectric insulation generally aligned with said floating gate;
• and
• i) an erasing means to remove electrical charges from said floating gate electrode and to detrap trapped electrical charges from said tunneling oxide insulation to improve a separation factor of a programmed threshold voltage and an erased threshold voltage of said non-volatile semiconductor memory device wherein said electrical charges trapped in the tunneling oxide are detrapped by the steps of:
• floating said source, drain, and first diffusion well,
• coupling the ground reference potential to said semiconductor substrate and second diffusion well,
• simultaneously coupling a third voltage source to apply a second relatively large negative voltage pulse to said control gate, and
• simultaneously coupling a fourth voltage source to the source to apply a second moderately large positive voltage to said source,
• and wherein said charges are removed from the floating gate subsequent to said removal of trapped charges by the steps of:
• coupling a first source to the first diffusion well to apply a first moderately large positive voltage pulse to the second diffusion well,
• simultaneously coupling a second voltage source to the control gate to apply a first relatively large negative voltage to the control gate,
• simultaneously coupling the ground reference potential to the semiconductor substrate, and simultaneously floating said drain and said first diffusion well.

A non-volatile semiconductor memory device comprising:

• a) a semiconductor substrate of a first conductivity type;
• b) a first diffusion well of a second conductivity type diffused into said semiconductor substrate,
• c) a second diffusion well of the first conductivity type diffused into said first diffusion well
• d) a plurality of memory cells arranged in an array wherein each cell comprises:
• a pair of diffusions of a second conductivity type spaced distally from one another to form a source region and a drain region within said second diffusion well,
• a tunneling oxide insulation disposed upon said semiconductor substrate in a region generally between the source region and drain region in correspondence with a channel region and having a thickness which allows tunneling of carriers there through,
• a floating gate electrode disposed upon said tunneling oxide insulation generally in correspondence with said channel region,
• an inter-poly dielectric insulation disposed upon said floating gate electrode to insulate said floating gate, and
• a control gate electrode disposed upon said inter-poly dielectric insulation generally aligned with said floating gate;
• and
• e) an erasing means to remove electrical charges from said floating gate electrode and to detrap trapped electrical charges from said tunneling oxide insulation to improve a separation factor of a programmed threshold voltage and an erased threshold voltage of said non-volatile semiconductor memory device wherein said electrical charges trapped in the tunneling oxide are detrapped by the steps of
• floating said source, drain, and first diffusion well,
• coupling the ground reference potential to said semiconductor substrate and second diffusion well,
• simultaneously coupling a third voltage source to apply a second relatively large negative voltage pulse to said control gate, and
• simultaneously coupling a fourth voltage source to the source to apply a second moderately large positive voltage to said source,
• and wherein charges are removed from the floating gate subsequent to the removal of the charges trapped in the tunneling oxide by the steps of:
• coupling a first source to the first diffusion well to apply a first moderately large positive voltage pulse to the second diffusion well,
• simultaneously coupling a second voltage source to the control gate to apply a first relatively large negative voltage to the control gate,
• simultaneously coupling the ground reference potential to the semiconductor substrate, and
• simultaneously floating said drain and said first diffusion well.

An erasing circuit to remove charges and to detrap charges from flash EEPROM cells, a source and a drain diffused within a first well of a first conductivity type which is diffused into a second well of a second conductivity type which is further diffused in to a semiconductor substrate of the first conductivity type, and a control gate, a floating gate, and a tunneling oxide disposed upon the semiconductor substrate, comprising:

• a) a first voltage source coupled to the control gate;
• b) a second voltage source coupled to the source region;
• c) a third voltage source coupled to the drain region;
• d) a fourth voltage source coupled to the semiconductor substrate;
• e) a fifth voltage source coupled to the first well;
• f) a sixth voltage source coupled to the second well
• g) an erasing control means coupled to the first, second, third, and fourth voltage sources to control said first, second, third, and fourth voltage sources, wherein a channel erasing to detrap said charges from the tunneling oxide is accomplished by the steps of:
• disconnecting said third and sixth voltage sources respectively from the drain and the second well to float said drain and second well,
• simultaneously forcing said fourth and fifth voltage source to apply the ground reference potential to said semiconductor substrate and to said first well,
• simultaneously forcing said first voltage source to apply a second relatively large negative voltage pulse to said control gate, and
• simultaneously forcing said second voltage source to apply a second moderately large positive voltage pulse to said source gate,
• and wherein a source erasing to remove charges from said floating gate subsequent to said detrapping is accomplished by:
• forcing said first voltage source to apply a first relatively large negative voltage pulse to the control gate of said EEPROM cell,
• simultaneously disconnecting said second voltage source to float the source of said EEPROM cell,
• simultaneously disconnecting said third voltage source to float the drain of said EEPROM cell,
• simultaneously disconnecting said sixth voltage source to float the first well,
• simultaneously forcing the fourth voltage sources to a ground reference potential to apply the ground reference potential to the semiconductor substrate and
• forcing said fifth voltage source to apply a first moderately large positive voltage pulse to the second well.