Fast EPROM array
AssigneeWaferScale Integration, Inc.
InventorBoaz Eitan
Life of this patent
Estimating the term…
Abstract
Each read line in a memory array containing a plurality of alternating bit lines and read lines with columns of memory cells therebetween, is broken into a plurality of electrically isolatable segments. As a result, the capacitance associated with each read line is significantly reduced and the speed of reading information from or writing information into a memory cell is significantly increased while at the same time not decreasing the density of the array.
Claims33
An EPROM array comprising:
- a semiconductor substrate;
- a plurality of floating gate transistors formed in and on said substrate, said floating gate transistors being arranged in rows and columns;
- a multiplicity of bit lines, BL0, . . . BLm, BL(m+1) . . . BLM wherein M+1 is an integer equal to the number of said bit lines, m is an integer given by 0.ltoreq.m.ltoreq.M, and BLm represents any one of said bit lines;
- and
- a plurality of read lines, RL0, . . . RLm, RL(m+1), . . . RL(M-1), wherein:
- said read lines are interleaved with said bit lines such that each read line RLm is placed between bit line BLm and bit line BL(m+1;
- each of said read lines is formed in said semiconductor substrate and is divided into a plurality of electrically-isolatable segments, each segment having two ends;
- and
- each of said bit lines is formed in said semiconductor substrate and is continuous.
An EPROM array comprising:
- a plurality of floating gate transistors arranged in rows and columns;
- a multiplicity of bit lines alternating with a plurality of read lines such that each read line is between two bit lines;
- a column of memory transistors placed between each adjacent bit line and read line;
- wherein each read line is broken into a plurality of electrically-isolatable segments and each bit line is continuous and formed by diffusion in a substrate.
An EPROM array comprising:
- a plurality of alternating non-segmented bit lines and segmented read lines wherein each read line is broken into a plurality of electrically isolatable segments formed by diffusion in a semiconductor substrate.
A common connection for an integrated-circuit memory, said memory having a control circuit, at least one memory cell array having column lines, and a programming circuit including at least first and second parts, comprising:
- at least one column of said at least one memory array selectively connected to a common conductor upon receiving at least a first signal from said control circuit;
- said first part of said programming circuit selectively connected to said common conductor upon receiving at least a second signal from said control circuit;
- and
- said second part of said programming circuit connected to said common conductor upon receiving at least a third signal from said control circuit.
A common connection for an integrated-circuit memory, said memory having a control circuit, a plurality of memory cell arrays having column lines, a sense amplifier circuit, and a programming circuit including at least first and second parts, comprising:
- at least one column of said at least one memory array selectively connected to a common conductor upon receiving at least a first signal from said control circuit;
- said first part of said programming circuit selectively connected to said common conductor upon receiving at least a second signal from said control circuit;
- and
- said second part of said programming circuit connected to said common conductor upon receiving at least a third signal from said control circuit;
- wherein said common conductor extends from a first area of said integrated-circuit memory to a second area of said integrated-circuit memory;
- wherein said sense amplifier circuit is selectively connected to said common conductor upon receiving at least a fourth signal from said control circuit;
- wherein said first and second parts of said programming circuit are located at opposite ends of said integrated-circuit memory;
- wherein said first part of said programming circuit provides a high voltage to a source-column line of said integrated-circuit memory;
- wherein said second part of said programming circuit provides a reference potential and a supply voltage to said common conductor;
- wherein said integrated-circuit memory is an electrically programmable read-only memory;
- and
- wherein said one column of one of said memory cell arrays is selectively connected to said common conductor upon receiving at least a fifth signal from said control circuit.
An integrated-circuit memory, said memory having a control circuit, at least one memory cell array having column lines, and a programming circuit including at least first and second parts, comprising:
- at least one column of said at least one memory array selectively connected to a common conductor upon receiving at least a first signal from said control circuit;
- said first part of said programming circuit selectively connected to said common conductor upon receiving at least a second signal from said control circuit;
- and
- said second part of said programming circuit connected to said common conductor upon receiving at least a third signal from said control circuit.
Dependencies are inferred from the claim text.