Integrated circuit memory devices having reconfigurable nonvolatile multi-bit memory cells therein and methods of operating same

An integrated circuit memory device, comprising:

• first and second pluralities of nonvolatile memory cells electrically coupled to respective first and second bit lines;
• first and second sense amplifiers having respective latches therein;
• first and second input/output lines electrically coupled to the latches of the first and second sense amplifiers, respectively;
• means for electrically coupling a sense node of said first sense amplifier to the first bit line, in response to a first address signal;
• means for electrically coupling a sense node of said second sense amplifier to the second bit line, in response to a second address signal;
• and
• means for electrically connecting the sense nodes of the first and second sense amplifiers together in response to a separation control signal.

An integrated circuit memory device, comprising:

• first and second pluralities of nonvolatile memory cells electrically coupled to respective first and second bit lines;
• first and second sense amplifiers having respective latches therein, electrically coupled to first and second input/output lines;
• means for electrically coupling a sense node of said first sense amplifier to the first bit line, in response to a first address signal;
• means for electrically coupling a sense node of said second sense amplifier to the second bit line, in response to a second address signal;
• and
• means, electrically coupled to the latches and sense nodes of said first and second sense amplifiers, for selectively configuring the memory cells as multi-bit memory cells by electrically connecting the sense nodes of the first and second sense amplifiers together in response to a separation control signal.

An integrated circuit memory device, comprising

• a plurality of nonvolatile memory cells;
• and
• means, coupled to the memory cells, for selectively configuring the memory cells as multi-bit memory cells during a multi-bit mode of operation and as single-bit memory cells during a single-bit mode of operation, and
• wherein said means for selectively configuring the memory cells comprises first and second sense amplifiers that can be electrically coupled to first and second strings of memory cells in the plurality thereof, and means, responsive to a separation control signal, for electrically connecting sense nodes of the first and second sense amplifiers together during the multi-bit mode of operation.

An integrated circuit memory device, comprising:

• first and second strings of nonvolatile memory cells;
• first and second bit lines electrically coupled to said first and second strings of nonvolatile memory cells;
• and
• a page buffer electrically connected to said first and second bit lines, said page buffer including first and second sense amplifiers having first and second sense nodes therein, respectively, and means, responsive to a separation control signal, for electrically connecting the first and second sense nodes together during a multi-bit mode of operation.