Floating gate memory array device with improved program and read performance

Abstract

A semiconductor memory array and method for use in a memory device in which the location of a memory cell in the array is specified by row address and column address decoders. The memory cells may be floating gate memory cells in which data is programmed by hot carrier injection and erased by Fowler-Nordheim tunneling. The array includes bit lines connected to the column address decoder, and word lines and N+ diffusion source lines connected to the row address decoder. Each memory cell has a gate connected to a word line, a drain connected to a bit line and a source connected to the N+ diffusion source line. A low resistance source line formed of metal II or other conductive material is arranged adjacent to each N+ source line and is electrically connected thereto at one or more locations via interconnecting straps. The low resistance source lines serve to reduce the voltage drop across the N+ diffusion source lines during program operations and provide an improved ground connection during read operations. The word lines are grouped into pairs of even and odd word lines and each pair makes up the minimum program unit or page. The page is also the minimum erase unit, such that adjacent even and odd word lines are erased simultaneously. The voltage applied to a given word line during a read operation may be supplied by a word line clamping circuit which limits gate disturbances resulting from fluctuations in supply voltage.

Dependencies are inferred from the claim text.