Methods and apparatus for fast check of floating point zero or negative zero

A method for performing floating point divide operations, comprising the steps of:

• supplying a floating point numerator and a floating point denominator to a hardware divider;
• performing a floating point divide operation on said floating point numerator and said floating point denominator with said hardware divider;
• supplying a floating point value of 0.0 having a sign bit and a modified floating point denominator to a hardware comparator, said modified floating point denominator comprising said floating point denominator having a modified sign bit, said modified sign bit being equal to the sign bit of said floating point value of 0.0;
• and
• performing a comparison of said floating point value of 0.0 and said modified floating point denominator, wherein a result of said comparison is indicative of a divide by zero operation and is independent of the sign of said floating point denominator.

Apparatus for performing floating point divide operations, comprising:

• a storage device containing a floating point numerator, a floating point denominator and a floating point value of 0.0, each having a sign bit;
• a divider receiving said floating point numerator and said floating point denominator, and performing a floating point divide operation on said floating point numerator and said floating point denominator;
• a first register coupled to said register file for receiving and holding said floating point value of 0.0;
• a second register coupled to said register file for receiving and holding a modified floating point denominator, said modified floating point denominator comprising said floating point denominator having a modified sign bit, said modified sign bit being equal to the sign bit of said floating point value of 0.0;
• a comparator for receiving said floating point value of 0.0 from said first register and said modified floating point denominator from said second register, and performing a comparison of said floating point value of 0.0 and said modified floating point denominator;
• and
• a logic element, responsive to a control signal indicative of said floating point divide operation, for providing said modified sign bit to said second register, wherein a result of said comparison is indicative of a divide by zero operation and is independent of the sign of said floating point denominator.

In a computer graphics system, apparatus for performing floating point divide operations, comprising:

• a storage device containing a floating point numerator, a floating point denominator and a floating point value of 0.0, each having a sign bit;
• a divider receiving said floating point numerator and said floating point denominator from said storage device, and performing a floating point divide operation on said floating point numerator and said floating point denominator;
• a comparator receiving said floating point value of 0.0 from said storage device and a modified floating point denominator, and performing a comparison of said floating point value of 0.0 and said modified floating point denominator, said modified floating point denominator comprising said floating point denominator having a modified sign bit, said modified sign bit being equal to the sign bit of said floating point value of 0.0;
• and
• a logic element, responsive to a control signal indicative of said floating point divide operation, for providing said modified sign bit, wherein a result of said comparison is indicative of a divide by zero operation and is independent of the sign of said floating point denominator.