Multilayer ceramic chip capacitor

Abstract

The invention provides a multilayer ceramic chip capacitor which satisfies X7R property or a temperature response of its capacitance and shows a minimal change of capacitance with time under a DC electric field, a long accelerated life of insulation resistance (IR) and good DC bias performance and also provides a multilayer ceramic chip capacitor which is resistant to dielectric breakdown in addition to the above advantages. In a first form of the invention, dielectric layers contain BaTiO.sub.3 as a major component and MgO, Y.sub.2 O.sub.3, at least one of BaO and CaO, and SiO.sub.2 as minor components in a specific proportion. In a second form, the dielectric layers further contain MnO and at least one of V.sub.2 O.sub.5 and MoO.sub.3 as minor components in a specific proportion. In the first form, the dielectric layer has a mean grain size of up to 0.45 .mu.m, and in an X-ray diffraction chart of the dielectric layer, a diffraction line of (200) plane and a diffraction line of (002) plane at least partially overlap one another to form a wide diffraction line which has a half-value width of up to 0.35.degree..

Dependencies are inferred from the claim text.