Multiplexed text data sampling circuit

#1. Field of the Invention

#The present invention relates to a multiplexed text data sampling circuit for use in a data extracting circuit of a multiplexed text broadcasting decoder.

#2. Description of the Prior Art

#Further objects and advantages of the present invention will be apparent from the following description of the preferred embodiments of the invention as illustrated in the accompanying drawings.

#FIG. 1 is a block diagram showing the structure of a multiplexed text data sampling circuit according to a first embodiment of the present invention;

#FIGS. 2a to 2g are timing charts for explaining the operation of the multiplexed text data sampling circuit according to the first embodiment of the present invention;

#Referring now to FIG. 1, it illustrates a block diagram showing the structure of a multiplexed text data sampling circuit according to a first embodiment of the present invention. In the figure, reference numeral 1 denotes a pre-sampling clock generating circuit for generating a pre-sampling clock signal PSCK from a clock signal CK, 2 denotes a start bit detecting circuit for detecting a start bit SB included in a text broadcasting signal and then delivering a start bit detecting signal indicating that it has detected the start bit, and 3 denotes a detecting signal inhibiting circuit for setting a mask period defined as a period of time during which the output of the start bit detecting signal is inhibited, and for disabling the start bit detecting signal which is delivered thereto during the mask period. Hereinafter, the output of the detecting signal inhibiting circuit 3 is referred to as a masked start bit detecting signal. Furthermore, 9 denotes a sampling clock generating circuit for generating a sampling clock signal SCK to sample data bits DB included in the text broadcasting signal in response to the masked start bit detecting signal from the detecting signal inhibiting circuit 3, and 10 denotes a data register for capturing the data bits DB in synchronization with the sampling clock signal SCK. A data sampling. unit according to this embodiment is composed of the sampling clock generating circuit 9 and data register 10.

#Next, a description will be made as to the operation of the multiplexed text data sampling circuit of this embodiment with reference to timing charts shown in FIGS. 2a to 2g. The process of extracting data SDA is the same as that in the prior art circuit mentioned above. The data SDA are applied to the multiplexed text data sampling circuit, as shown in FIG. 1. Then, the pre-sampling clock generating circuit 1 and start bit detecting circuit 2 operate in the same manner as the prior art circuits mentioned above, as shown in FIGS. 2c to 2e, and the start bit detecting circuit 2 outputs a start bit detecting signal.

#The detecting signal inhibiting circuit 3 receives a horizontal synchronizing signal as well as a clock signal CK, and generates a mask signal having an active time period associated with a period of time between the instant when the horizontal synchronizing signal is delivered thereto and the instant when the start bit is generated. In this embodiment, a mask signal having an active time period between the instant when the horizontal synchronizing signal is delivered thereto and the instant when a clock run-in interval CRI is concluded is generated, as shown in FIG. 2e. Although the detecting signal inhibiting circuit 3 receives the start bit detecting signal from the start bit detecting circuit 2, it prevents the start bit detecting signal from passing therethrough during the active time period of the mask signal. During the nonactive time period of the mask signal, the start bit detecting signal is allowed to pass through the detecting signal inhibiting circuit 3.