Method and a system for the nonlinear storage of a texture map within a linear memory device

A system for the nonlinear storage of a plurality of data points of a texture map matrix, the system comprising:

• a linear memory device including a plurality of memory locations;
• and
• a processing circuit coupled to said linear memory device, said processing circuit including
• a determining means for determining the maximum number of the data points capable of being written to each memory location during a write cycle to said linear memory device,
• a matrix generating means for grouping the plurality of data points into at least two storage matrices based on the maximum number of the data points determined by said determining means, each storage matrix including at least one pair of adjacent data points from two adjacent rows of the texture map matrix, and
• a storing means for writing each storage matrix from said matrix generating means to a distinct memory location of said linear memory device.

A method for the nonlinear storage of a plurality of data points of a texture map matrix within a plurality of memory locations of a linear memory device, the method comprising the steps of:

• (a) subdividing adjacent rows of the texture map matrix into a plurality of multi-data point groups, each multi-data point group having a plurality of adjacent rows of data points;
• (b) placing said multi-data point groups adjacent to each other in order to create a linear string;
• and
• (c) writing said linear string to the plurality of memory locations.

A system for the nonlinear storage of a plurality of data points of a texture map matrix, the system comprising:

• a linear memory device including a plurality of memory locations;
• a convoluting circuit coupled to said linear memory device, said convoluting circuit to rearrange the plurality of data points from the texture map matrix into a linear string by subdividing adjacent rows of the texture map matrix into a plurality of multi-data point groups, and by placing said multi-data point groups adjacent to each other;
• and
• a writing circuit coupled to said processor circuit and to said linear memory to write said linear string from said convoluting circuit to said linear memory device.