US 5,861,879 A · Video signal processing device for writing and reading a video signal with respect to a memory according to different clocks, while preventing a write/read address pass-by in the memory

Abstract

An input video signal is written into alternate field memories M1 and M2, according to a timing clock from an input video clock generator. A display video signal is alternately read from those field memories, according to a timing clock from a display video clock generator. In switching a read memory, an address observation circuit judges whether or not a read/write address passes by a write/read address, referring to the condition of reading and writing operations. In this event, the circuit makes a judgement, based on the lag between a vertical synchronizing signals of an input video signal and of a display video signal, and a change of the lag with time. If it is judged that one address will pass by the other, the same read/write memory is again accessed for reading/writing. With this arrangement, there is provided a circuit having a relatively simple structure for preventing a match of read and write addresses.

Claims10

Dependent claims

A video processing device for obtaining a display video signal according to a synchronizing signal different from a synchronizing signal for an input video signal by writing an input video into a memory according to a write clock and reading a video signal from a memory according to a read clock, comprising:

a lag amount detection circuit for detecting a lag amount between a vertical synchronizing signal of a display video signal and a vertical synchronizing signal of an input video signal;
a varied lag amount detection circuit for detecting an amount varied with time of the lag amount;
a comparison circuit for comparing the lag amount detected and the amount varied with time of the lag amount;
and
a control circuit for controlling an access to a memory during a video display unit period wherein the sequence of a vertical synchronizing signal of an input video signal and a vertical synchronizing signal of a display video signal is about to be inverse, based on a result by the comparison circuit.

2 more elements

A video signal processing device for obtaining a display video signal according to a synchronizing signal different from a synchronizing signal for an input video signal by writing an input video signal into a memory according to a write clock and reading a video signal from a memory according to a read clock, comprising:

two memories each accessed alternately for writing an input video signal or reading a display video signal;
a judgement circuit for judging whether or not one of read/write addresses will pass by one of read write addresses when accessing a same memory, wherein,
upon detection that one address will pass by another address, the same memory is repeatedly accessed for data reading to writing, prohibiting a change of a read or write memory;
wherein the judgement circuit includes a lag detection circuit for detecting a previous lag amount and a current lag amount regarding two adjacent vertical synchronizing signals of an input video signal or a display video signal;
a varied lag amount detection circuit for detecting an amount varied with time of a lag amount, based on a difference between the previous lag amount and the current lag amount;
and
a comparison circuit for comparing the current lag amount and an amount varied with time of a lag amount currently detected and judging whether or not a preceding-following relationship between vertical synchronizing signals of an input video signal and a display video signal will be reversed in accordance with a variation in a lag amount until next detection.

4 more elements

Dependencies are inferred from the claim text.

Video signal processing device for writing and reading a video signal with respect to a memory according to different clocks, while preventing a write/read address pass-by in the memory

Life of this patent

Video signal processing device for writing and reading a video signal with respect to a memory according to different clocks, while preventing a write/read address pass-by in the memory

Life of this patent

Abstract

Claims10