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US 5,861,765 AGranted
Analogue delay circuit with a constant delay time
AssigneeNEC Corporation
InventorMasahiko Hirai
Life of this patent
Estimating the term…
Abstract
In an analogue delay circuit which is constructed from a p-type MOS transistor and an n-type MOS transistor and which includes an inverter gate for inputting input signals and a capacitance having one electrode connected to ground and the other electrode connected to the drain of the inverter gate, the gate potential of the n-type MOS transistor is limited by means of a clamping circuit so as not to exceed the minimum operating voltage, and the potential of a line connected to an electrode of the capacitance is limited by another clamping circuit so as to not exceed the minimum operating voltage.
Claims6
An analogue delay circuit comprising:
- a first p-type MOS transistor and a first n-type MOS transistor connected in series to each other between a power source and a ground;
- means for transmitting an input signal of said analog delay circuit to the gate of said first p-type MOS transistor;
- capacitance means having a first and a second electrode, the first connected to said ground;
- first clamping means having an input connected to the drain of said first p-type MOS transistor and the drain of said first n-type MOS transistor, and an output connected to the second electrode of said capacitance means, for limiting a potential of said capacitance means to below a fixed potential;
- second clamping means having an input connected to the input signal of said analog delay circuit and an output connected to the gate of said first n-type MOS transistor, for limiting a gate potential of said first n-type MOS transistor to below a fixed potential.
2 more elements
An analogue delay circuit comprising:
- a first p-type MOS transistor and a first n-type MOS transistor connected in series to each other between a power source and a ground;
- means for transmitting an input signal of said analog delay circuit to the gate of said first p-type MOS transistor;
- capacitance means having a first electrode and a second electrode, the first electrode being connected to ground;
- first clamping means having an input connected to the drain of said first p-type MOS transistor and the drain of said first n-type MOS transistor, and an output connected to the second electrode of said capacitance means, for limiting a potential of said capacitance means to below a fixed potential;
- and
- second clamping means having an input connected to the input signal of said analog delay circuit and an output connected to the gate of said first p-type MOS transistor, for limiting a gate potential of said first p-type MOS transistor to above a fixed potential.
3 more elements
An analogue delay circuit comprising:
- a first p-type MOS transistor and a first n-type MOS transistor connected in series to each other between a power source and a ground;
- a first inverter gate for inverting an input signal of said delay circuit and outputting the inverted input signal to the gate of said first p-type MOS transistor;
- a second inverter gate for inverting said input signal;
- capacitance means having a first electrode and a second electrode, said first electrode being connected to said ground;
- first clamping means having an input connected to the drain of said first p-type MOS transistor and the drain of said first n-type MOS transistor, and having an output connected to the second electrode of said capacitance means, for limiting a potential of said other electrode to below a fixed potential;
- second clamping means having an input receiving the inverted input signal of said second inverter gate and an output connected to the gate of said first n-type MOS transistor, and for limiting gate potential of said first n-type MOS transistor to below a fixed potential;
- a third inverter gate having an ON-state depression n-type MOS transistor and a second n-type MOS transistor connected in series to each other between a power source and a ground, the gate of said second n-type MOS transistor being connected to the second electrode of said capacitance means, the drains of said ON-state depression n-type MOS and second n-type MOS transistor being an output of said third inverter gate;
- a fourth inverter gate for inverting a signal on the output of said third inverter gate.
5 more elements
An analogue delay circuit comprising:
- a first p-type MOS transistor and a first n-type MOS transistor connected in series to each other between a power source and a ground;
- a first inverter gate for inverting an input signal of said delay circuit;
- a second inverter gate for inverting said input signal and outputting the inverted input signal to the gate of said first n-type MOS transistor;
- capacitance means having a first electrode and a second electrode, the first electrode being connected to the power source;
- first clamping means having an input connected to the drain of said first p-type MOS transistor and to the drain of the first n-type MOS transistor, and having an output connected to the second electrode of said capacitance means, for limiting a potential of said capacitance means to below a fixed potential;
- second clamping means for receiving an inverted input signal from said first inverter gate, and having an output connected to the gate of said first p-type MOS transistor, for limiting a gate potential of said p-type MOS transistor to above a fixed potential;
- third inverter gate consisting of a second p-type MOS transistor and a resistance connected in series to each other between a power source and a ground, the gate of said second p-type MOS transistor being connected to the second electrode of said capacitance means, the connection between said second n-type MOS transistor and said resistance being an output of said third inverter gate;
- and
- fourth inverter gate for inverting a signal on the output of said third inverter gate.
6 more elements
Dependencies are inferred from the claim text.