US 5,861,764 A · Clock skew reduction using spider clock trace routing

Abstract

A technique for reducing skew between clock signals in a digital system requiring multiple clock signals. The system preferably is implemented on a printed circuit board. An oscillator circuit provides a periodic signal to a clock buffer which generates multiple periodic clock signals. The clock signals are provided to various destination points on the printed circuit board. The rising and falling edges of each clock signal generated by the clock buffer do not occur precisely at the same time as the rising and falling edges of the other clock signals. This misalignment of clock edges, or skew, is detrimental to system performance, but is reduced substantially by connecting all of the clock buffer's output clock signals together at a single physical point or node. Accordingly, the printed circuit board traces carrying each of the clock signals are routed to a single point node. A single point node is used to reduce skew caused by the clock buffer. Single point nodes also may be used at various locations on the printed circuit board to reduce skew caused by differences in the lengths of the traces carrying the clock signals.

Claims13

Dependent claims

A clock circuit providing a plurality of clock signals, said clock circuit reducing buffer-to-buffer skew associated with the plurality of clock signals, comprising:

an oscillator circuit providing a periodic signal;
a clock buffer receiving said periodic signal from said oscillator circuit and generating the plurality of clock signals;
a set of conductive paths connecting said clock buffer to a common single point node and at least one of the plurality of clock signals being transmitted on at least one of the set of conductive paths.

Dependencies are inferred from the claim text.

Clock skew reduction using spider clock trace routing

Life of this patent

Clock skew reduction using spider clock trace routing

Life of this patent

Abstract

Claims13