Threshold voltage scalable buffer with reference level
AssigneeMicron Technology, Inc.
InventorHuy Thanh Vo
Life of this patent
Estimating the term…
Abstract
A buffer circuit (10). The buffer circuit (10) includes a first inverter (12) with a first current limiter (18) that limits the standby current used by the first inverter (12). Further, the buffer circuit (10) includes a second inverter (14) that is coupled to an output of the first inverter (12). The input buffer (10) converts a first logic level of an input signal provided to the first inverter (12) to a second logic level at an output of the second inverter (14). The buffer circuit (10) also includes a second current limiting circuit (16) that is coupled between the first and second inverters (12 and 14) to further limit the standby current in the buffer circuit (10).
Claims13
A method for converting a signal between first and second logic families with reduced standby current, the method comprising:
- inverting an input signal of a first logic family with a first inverter;
- inverting the output of the first invertor with a second inverter so as to produce an output signal with a logic level of the second logic family;
- feeding the output of the second inverter back to current limiting transistors of the first inverter to limit the standby current of the first inverter;
- and
- selectively applying reference voltages to transistors coupled to the output of the first inverter and to the input of the second inverter in a standby current path based on the output of the second inverter so as to further limit the standby current.
A buffer circuit, comprising:
- a first inverter with a first current limiter that limits the standby current used by the first inverter;
- a second inverter coupled to an output of the first inverter so as to convert a first logic level of an input signal provided to the first inverter to a second logic level at an output of the second inverter;
- a second current limiting circuit coupled to the output of the first inverter and to the input of the second inverter to further limit the standby current in the buffer;
- and
- wherein the first and second current limiting circuits are controlled by a feedback signal from the output of the second inverter.
A buffer that converts a signal between first and second logic families with reduced standby current, the buffer comprising:
- first means for inverting an input signal of a first logic family;
- second means for inverting the output of the first means for inverting so as to produce an output signal with a logic level of the second logic family;
- means for feeding the output of the second means for inverting back to current limiting circuits of the first means for inverting to limit the standby current;
- and
- means for selectively applying reference voltages to transistors coupled to the output of the means for inverting and to the input of the second means for inverting in a standby current path based on the output of the second means for inverting so as to further limit the standby current.
A buffer circuit, comprising:
- a first inverter with a first current limiter that limits the standby current used by the first inverter;
- a second inverter coupled to an output of the first inverter so as to convert a first logic level of an input signal provided to the first inverter to a second logic level at an output of the second inverter;
- a second current limiting circuit coupled to the output of the first inverter and to the input of the second inverter to further limit the standby current in the buffer;
- a precharge circuit coupled between the output of the second inverter and the input to the second inverter that precharges the input to the second inverter based on the output of the second inverter;
- and
- wherein the first and second current limiting circuits are controlled by a feedback signal from the output of the second inverter.
Dependencies are inferred from the claim text.