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US 5,861,762 AGranted
Inverse toggle XOR and XNOR circuit
AssigneeSun Microsystems, Inc.
InventorIvan E. Sutherland
Life of this patent
Estimating the term…
Abstract
A four transistor XOR or XNOR gate includes an inverting stage and a non-inverting stage. The transistors in each stage are coupled so as to enable changing inputs and existing inputs to drive the output in the same direction. The XOR gate and XNOR gate take advantage of a known order or inputs to reduce the delay of the gate.
Claims13
A logic gate for producing a first output logic signal representing a logical operation of a first logic signal and a second logic signal, the logic gate comprising:
- a first input terminal receiving the first logic signal;
- a second input terminal receiving the second logic signal;
- a third input terminal receiving a first inverted logic signal representing the logical inverse of the first logic signal;
- a fourth input terminal for receiving a second inverted logic signal representing the logical inverse of the second logic signal;
- a non-inverting stage including
- a first transistor of a first type having a first channel coupled at a first end to the first input terminal and having a first gate coupled to the fourth input terminal, and
- a second transistor of a second type, different from the first type, having a second channel coupled between a second end of the first channel and the second input terminal, and having a second gate coupled to the first input terminal;
- an inverting stage including
- a third transistor of the first type having a third channel coupled at a first end to the third input terminal and a third gate coupled to the second input terminal, and
- a fourth transistor of the second type having a fourth channel coupled between a second end of the third channel and the fourth input terminal, and having a fourth gate coupled to the third input terminal;
- and
- a first output terminal coupled to the junction of the first and second channels and to the junction of the third and fourth channels, for providing the first output logic signal.
9 more elements
A computer system comprising:
- a memory;
- one or more user input devices;
- one or more output devices;
- and
- a processor which is operatively coupled to the memory, the user input devices, and the output devices and which includes
- a logic gate for producing a first output logic signal representing a logical operation of a first logic signal and a second logic signal, the logic gate including
- a first input terminal receiving the first logic signal;
- a second input terminal receiving the second logic signal;
- a third input terminal receiving a first inverted logic signal representing the logical inverse of the first logic signal;
- a fourth input terminal receiving a second inverted logic signal representing the logical inverse of the second logic signal;
- a non-inverting stage including
- a first transistor of a first type having a first channel coupled at a first end to the first input terminal and having a first gate coupled to the fourth input terminal, and
- a second transistor of a second type, different from the first type, having a second channel coupled between a second end of the first channel and the second input terminal, and having a second gate coupled to the first input terminal;
- an inverting stage including
- a third transistor of the first type having a third channel coupled at a first end to the third input terminal and a third gate coupled to the second input terminal, and
- a fourth transistor of the second type having a fourth channel coupled between a second end of the third channel and the fourth input terminal, and having a fourth gate coupled to the third input terminal;
- and
- a first output terminal coupled to the junction of the first and second channels and to the junction of the third and fourth channels, for providing the first output logic signal;
- and
- a plurality of logic elements coupled to the first, second, third, and fourth input terminals and the first output terminal of the logic gate.
17 more elements
A method for operating a logic gate having
- a first input terminal receiving a first logic signal,
- a second input terminal receiving a second logic signal,
- a third input terminal receiving a logical inverse of the first logic signal,
- a fourth input terminal receiving a logical inverse of the second logic signal
- a non-inverting stage connected between the first and second input terminals and including a first transistor of a first type connected in series with a second transistor of a second type, a gate of the first transistor being coupled to the fourth input terminal, and a gate of the second transistor being coupled to the first input terminal,
- an inverting stage connected between the third and fourth input terminals and including a third transistor of the first type connected in series with a fourth transistor of the second type, a gate of the third transistor being coupled to the second input terminal, and a gate of the fourth transistor being coupled to the third input terminal, and
- a first output terminal coupled to the junction of the first and second transistors and to the junction of the third and fourth transistors,
- the method comprising the steps of:
- driving the first output terminal to a first state when the first logic signal and second logic signal are both at the same state;
- and
- driving the first output terminal to a state that is the inverse of the first state when the first logic signal is at a different state from the second logic signal.
8 more elements
Dependencies are inferred from the claim text.