Tolerance input/output circuit operating in single power supply

Abstract

A tolerance input/output circuit is provided for operating as the interface of a device to which a predetermined voltage or more cannot be applied to make it operate, depending on whether it is in an input mode or an output mode. The circuit includes an internal power supply, a Y gate signal generator, a kilpoly signal generator, a P gate signal generator and an output circuit. The Y gate signal generator receives an external pad signal of a high level, then generates a signal of an internal power supply level. The kilpoly signal generator generates the signal of the internal power supply level when the pad signal is at a low level, and generates the pad signal when the pad signal is at a high level. In an input mode, the P gate signal generator generates as a P gate signal the signal of the internal power supply level, when the pad signal is at a low level, and the pad signal, when the pad signal is of a high level. In the output mode, the P gate signal generator generates as a P gate signal the internal power supply level when the pad signal is at a low level, and a signal of a low level when the pad signal is at a high level. The output circuit generates a signal which has a high impedance in the input mode and which normally operates to supply the internal power supply level of a high level in the output mode, as the pad signal. The output of the kilpoly signal generator is fed back to the substrates of the PMOS transistors included in the kilpoly signal generator, the P gate signal generator and the output circuit.

Dependencies are inferred from the claim text.