US 5,861,668 A · Semiconductor package

Abstract

A semiconductor package of the present invention includes a paddle layer having a metal wiring pattern formed therein, semiconductor chips bonded on at least one surface of the paddle layer. A plurality of wires electrically connecting a plurality of chip pads formed on the semiconductor chips with the paddle layer. Each lead includes a first lead bonded to a surface of the paddle layer and a second lead which is at least partially exposed. A conductive adhesive bonds the paddle layer to the first leads and a molding resin comprises the body of the package. The semiconductor package of the above construction has various advantages compared to conventional packages. The occupying area rate can be minimized, and an undesired curving of the lead can be prevented. Further, since the semiconductor chip can be bonded on both surfaces of the paddle layer, an integrated semiconductor package can be achieved.

Claims23

Dependent claims

A chip package, comprising:

a first chip having a plurality of chip pads;
a paddle layer having first and second surfaces, said paddle layer having a plurality of first connection pads, a plurality of second connection pads, and electrically conductive media coupling corresponding first and second connection pads to each other;
means for attaching said first chip to said first surface of said paddle layer, and conductively coupling corresponding chip pads to corresponding first connection pads;
a plurality of leads with first and second surfaces, wherein each of the leads has an internal portion and a bottom portion, and wherein said second surface of the bottom portion of each of the leads is exposed on a bottom surface of the chip package;
means for connectively mounting said second connection pads to the first surface of said internal portions of corresponding leads;
and
molded resin for packaging said first chip, paddle layer, attaching means, plurality of leads and mounting means.

4 more elements

Dependencies are inferred from the claim text.

Semiconductor package

Life of this patent

Semiconductor package

Life of this patent

Abstract

Claims23