Microcontroller configured to indicate internal memory accesses externally

Abstract

A microcontroller integrates a memory accessible by the processor core. Additionally, the microcontroller provides an indication upon an external bus that memory accesses mapped to the integrated memory are occurring, independent of the enablement status of the memory. The indication provides a ready identification of internal access cycles. In one embodiment, the indication is multiplex with a control signal upon the external bus. The microcontroller further employs a show read bus transfer, which may be optionally enabled by the user. The show read bus transfer transmits upon the external bus the read data being provided from the internal memory to a core. The cycle is presented with identical functional timing to normal read cycles. Additionally, the A/C timings of the show read bus transfer are consistent with external read transfers. Therefore, external circuitry (such as an in-circuit emulator) may capture the data from the show read bus transfer using the same circuitry used to capture external read data. The show read bus transfer may be enabled by setting a configuration register bit within the microcontroller, or by asserting a signal upon a predefined pin at the conclusion of reset of the microcontroller. By providing the predefined pin for activating the show read mode of the microcontroller, the microcontroller may be placed into show read mode for debug purposes without changing the instruction code being executed thereon.

Dependencies are inferred from the claim text.