US 5,860,154 AGranted

Method and apparatus for calculating effective memory addresses

AssigneeIntel Corporation

InventorsJeffrey M. Abramson, Haitham Akkary, Andrew F. Glew, Glenn J. Hinton, Kris G. Konigsfeld, Paul D. Madland, Mark A. Timko

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Abstract

A macro instruction is provided for a microprocessor which allows a programmer to specify a base value, index, scale factor and displacement value for calculating an effective address and returning that result in a single clock cycle. The macro instruction is converted into a micro operation which is provided to the single-cycle execution unit with the required source operands for performing the calculation. Within the single-cycle execution unit, the index and scale factor are provided to a left shifter for multiplying the two values. The result of the left shift operation is added to the sum of the base and displacement. This results in the effective address which is then returned from the single-cycle execution unit to a predetermined destination. This provides for the calculation of an effective address in a single cycle pipeline execution unit that is independent of the memory system execution units.

Claims14

Dependent claims

A processor having more than one execution unit, said processor comprising:

a single-cycle arithmetic execution unit, the single-cycle arithmetic execution unit comprising
integer calculation logic, said integer calculation logic for performing integer mathematical and logic operations,
a first effective address generation logic for calculating a first effective memory address determined by a first base value, a first index, a first scale factor and a displacement value, said
first effective address generation logic comprising
a multiplier for multiplying the first index by the first scale factor to produce a scaled index value,
an adder coupled to the multiplier for adding the scaled index value to the first base value and to the first displacement value to produce said first effective memory address;
and
a multiple-cycle memory access execution unit, said multiple-cycle memory access execution unit comprising
a second effective address generation logic for calculating a second effective memory address determined by a second base value, a second index, a second scale factor and a second displacement value,
a segment violation checker, said segment violation checker for determining if said second effective memory address is a legal memory address,
memory access logic, said memory access logic for accessing data located at said second effective memory address.

8 more elements

A microprocessor, the microprocessor being coupled to a memory, the memory for storing data according to a segmented memory configuration, the microprocessor comprising:

a reservation station for scheduling and dispatching computer instructions with source operands to execution units;
a first arithmetic execution unit coupled to receive instructions and source operands from the reservation station, the first arithmetic execution unit for initiating memory operations for the microprocessor including calculating a first effective address in accordance with the segmented memory configuration, checking said first effective memory address for segment violations, and accessing memory using said first effective memory address, the first execution unit requiring more than a single clock cycle to return memory result data;
a second arithmetic execution unit coupled to receive instructions and source operands from the reservation station, the second arithmetic execution unit for calculating a second effective memory address in accordance with the segmented memory configuration, the second execution unit requiring only a single clock cycle to return said second effective memory address, the second execution unit also performing integer logic operations;
and
a reorder buffer coupled to the first and second arithmetic execution units for buffering result data from the first and second arithmetic execution units until the result data is ready for retirement.

2 more elements

A computer system comprising:

an input/output means providing a communicating interface;
a memory means coupled to the input/output means for storing instructions and computer data;
data input means coupled to the input/output means for providing data input and data output to interface the computer system with a computer user;
and
microprocessor means coupled to the input/output means for executing instructions and processing computer data, the microprocessor means operating in accordance with segmented memory protocol, the microprocessor including:
a reservation station for scheduling and dispatching computer instructions with source operands to execution units;
a first arithmetic execution unit coupled to receive instructions and source operands from the reservation station, the first arithmetic execution unit for initiating memory operations for the microprocessor including calculating a first effective memory address in accordance with the segmented memory configuration, checking said first effective memory address for segment violations, and accessing memory using said first effective memory address, the first arithmetic execution unit requiring more than a single clock cycle to return memory result data;
a second arithmetic execution unit coupled to receive instructions and source operands from the reservation station, the second arithmetic execution unit for calculating a second effective memory address in accordance with the segmented memory configuration, the second arithmetic execution unit requiring only a single cycle to calculate and return said second effective memory address, the second arithmetic execution unit also performing integer logic operations;
and
a reorder buffer coupled to the first and second arithmetic execution units for buffering result data from the first and second arithmetic execution units until the result data is ready for retirement.

7 more elements

Dependencies are inferred from the claim text.