Asynchronous transfer mode cell processing system with cell buffer space gathering

Abstract

Methods and apparatus for processing cells in an asynchronous transfer mode (ATM) communication system. An ATM cell processor provides a cell buffer RAM (CBR) memory space gathering protocol which allows unused portions of a number of cell buffers to be addressed as a contiguous virtual memory space. The space gathering protocol may utilize a CPU or direct memory access (DMA) controller in an ATM cell processor to set a gather bit appended to a virtual CBR address. An address generator in the CBR detects the gather bit and translates those virtual addresses which include a set gather bit to physical addresses into the CBR memory space. The translation is performed by setting certain bits of the physical address to predetermined states to reach the unused 8 bytes at the bottom of any given 64-byte cell buffer, and shifting certain bits of the virtual address to other positions in the physical address to move from cell buffer to cell buffer in the contiguous virtual space. Multiple gather spaces may be supported in alternative embodiments by using a different number of gather bits.

Dependencies are inferred from the claim text.