Method and apparatus for replacement of entries in a translation look-aside buffer

In a computer processor that processes architectural instructions using microinstruction routines, an apparatus for translating a virtual address into a physical address, said apparatus comprising:

• a virtual address array, said virtual address array comprising a plurality of virtual address array entries wherein each virtual address array entry has a virtual address tag field, said virtual address array fully associative such that any virtual address may occupy any virtual address array entry;
• and
• a physical address array, said physical address array comprising a plurality of physical address array entries wherein each physical address array entry is coupled to a corresponding virtual address array entry by a match line, each of said physical address array entries comprising:
• a physical address field;
• a locked bit, said locked bit set when a microinstruction routine accesses said physical address entry, said locked bit reset when said microinstruction routine terminates.

A method of replacing entries in a translation look-aside buffer, said method comprising the steps of:

• examining a locked bit and an access bit on a translation look-aside buffer entry;
• replacing said translation look-aside buffer entry if said lock bit and said access bit are clear;
• clearing the access bit in all translation look-aside buffer entries if all said entries have either an access bit or a locked bit set;
• setting the locked bit in a particular translation look-aside buffer entry if a microinstruction routine accesses said translation look-aside buffer entry;
• clearing said locked bit in said translation look-aside buffer entry when said microinstruction routine terminates.