US 5,860,144 A · Addressing method and system for providing access of a very large size physical memory buffer to a number of processes

Abstract

An addressing method and system for accessing a very large size physical buffer by a number of processes. The novel system is applicable within a computer system having an n-bit computer operating system (e.g., where n is 16, 32, 64, etc.). The addressing method allocates a relatively small window of virtual address space, for each software process, which is used to access the very large physical buffer using a relatively small amount of operating system memory overhead. A page frame number (PFN) table of the system address space maintains a listing of physical memory pages used to define the very large physical buffer. The PFN table is used by each process to translate between a relative page number (RPN) and an address of a physical memory page containing the record. The virtual address space ("window") of each process is used to access the physical memory buffer and contains a hash table, a virtual access control block (VACB) free list, and a VACB table. Entries of the VACB table indicate addresses of virtual memory for the process. Each process also has an associated private page table entry (PTE) table which maintains a mapping between its virtual pages and the physical pages. To map a record, its RPN is determined and used to obtain the address of the physical page(s) in which the record resides. The free list supplies an entry of the VACB table containing a virtual address for the record. The virtual address and the physical address are mapped into the PTE table.

Claims28

Dependent claims

In a computer system having a processor coupled to a bus and a memory coupled to said bus, an addressing system for providing a process with access to a large physical memory space, said addressing system comprising:

(a) a first table comprising a plurality of entries, each entry corresponding to a page of said physical memory space, said first table stored in said memory;
(b) a virtual window associated with said process and representing a relatively small amount of virtual address space compared to said physical memory space, said virtual window comprising a control block table stored in said memory, said control block table comprising a plurality of control block entries, each control block entry representing a page of virtual memory within said virtual window;
and
(c) a page table entry data structure stored in said memory and corresponding to said process, said page table entry data structure comprising a plurality of entries, each entry for mapping a page of virtual memory of said process to a page of said physical memory space, wherein data records of said physical memory space are mapped into said virtual window of said process by associating, within said entries of said page table entry data structure, physical page addresses of said data records with vacant virtual page addresses of said virtual window.

1 more element

In a computer system having a processor coupled to a bus and a memory coupled to said bus, an addressing system for providing a plurality of processes with access to a large physical memory space of said memory, said addressing system comprising:

(a) a first table comprising a plurality of entries, each entry corresponding to a page of said physical memory space;
(b) a plurality of virtual windows each associated with a particular process of said plurality of processes and each representing a relatively small amount of virtual address space in relation to said physical memory space, each of said virtual windows comprising:
(1) a control block table comprising a plurality of control block entries, each control block entry representing a page of virtual memory within said virtual window;
and
(2) a control block free list indicating vacant entries within said control block table;
and
(c) a plurality of page table entry data structures each associated with a particular process of said plurality of processes, each of said page table entry data structures comprising a plurality of entries, each entry for mapping a particular page of virtual memory of said page table entry data structure's particular process to a page of said physical memory space, and
wherein data records of said physical memory space are mapped into said virtual windows of said process by associating, within said entries of said page table entry data structures, physical page addresses of said data records with vacant virtual page addresses of said virtual windows.

5 more elements

In a computer system having a processor coupled to a bus, a disk coupled to said bus, and a physical memory coupled to said bus, an addressing method for providing access of a very large physical memory space to a plurality of processes, said addressing method comprising the computer implemented steps of:

generating a page table having a plurality of entries, each entry corresponding to at least one page within said large physical memory space, said plurality of entries defining a physical buffer;
loading a set data records associated with a database application into said physical buffer;
generating a plurality of virtual windows within said computer system, each of said virtual windows associated with a process of said plurality of n processes, each of said virtual windows providing its associated process with a virtual address space with which said associated process can access said physical buffer, said virtual address space being substantially smaller than said physical buffer;
and
mapping a particular data record of said physical buffer into a virtual address space associated with a particular virtual window of said plurality of virtual windows, said step of mapping providing a particular process associated with said particular virtual window with access to said data record within said physical buffer.

2 more elements

A computer system comprising a processor coupled to a bus, a disk coupled to said bus, and a computer readable memory unit coupled to said bus, said computer readable memory unit containing a computer program of instructions for causing said computer system to implement an addressing method for providing access of a very large physical memory space to a plurality of n processes, said addressing method comprising the computer implemented steps of:

generating a page table having a plurality of entries, each entry corresponding to at least one page within said large physical memory space, said plurality of entries defining a physical buffer;
loading a set of data records associated with a database application into said physical buffer;
generating a plurality of virtual windows within said computer system, each of said virtual windows associated with a process of said plurality of n processes, each of said virtual windows providing its associated process with a virtual address space with which said associated process can access said physical buffer, said virtual address space being substantially smaller than said physical buffer;
and
mapping a particular data record of said physical buffer into a virtual address space associated with a particular virtual window of said plurality of virtual windows, said step of mapping providing a particular process associated with said particular virtual window with access to said data record within said physical buffer.

2 more elements

Dependencies are inferred from the claim text.

Addressing method and system for providing access of a very large size physical memory buffer to a number of processes

Life of this patent

Addressing method and system for providing access of a very large size physical memory buffer to a number of processes

Life of this patent

Abstract

Claims28