Method and apparatus for mapping the memory system of a computer for maximizing memory usage

A computer system, comprising:

• a host bus;
• a processor coupled to said host bus that asserts addresses between a lowest address and a highest address defining at least 4 gigabytes of memory area;
• a plurality of host peripheral component interconnect (PCI) buses including a primary host PCI bus, each coupled to said host bus via a corresponding host-PCI bridge;
• a plurality of subordinate PCI buses, each coupled to one of said plurality of host PCI buses via a corresponding PCI-PCI bridge;
• a plurality of PCI devices, each coupled to one of said plurality of host and subordinate PCI buses and each having associated memory, said associated memory of each of said plurality of PCI devices being mapped in descending order in said memory area beginning at a predetermined upper PCI memory address and ending at a lower PCI address below said predetermined upper PCI memory address, and starting with a highest numbered PCI host bus and its subordinate PCI buses, if any, and continuing in reverse order of said plurality of PCI host buses and ending with said primary host PCI bus and its subordinates, if any;
• and
• system memory devices coupled to said host bus mapped between said lowest address and said upper system memory address.

A method of mapping a memory system of a computer having a host bus and a predetermined memory space with a lowest address and a highest address, comprising steps of:

• identifying all peripheral component interconnect (PCI) buses coupled through the host bus of the computer including any host PCI buses and any subordinate PCI buses coupled behind the host PCI buses;
• enumerating the PCI buses;
• and
• allocating and initializing the memory of each PCI device coupled to the PCI buses within a PCI memory location starting with the highest numbered PCI host bus and its subordinate PCI buses, if any, and continuing in reverse order of PCI host buses and ending with a primary host PCI bus and its subordinates, and progressing in descending order in the PCI memory location beginning at an upper PCI memory address below the highest address and ending at a lower PCI address below the upper PCI memory address.