US 5,860,138 AGranted

Processor with compiler-allocated, variable length intermediate storage

AssigneeInternational Business Machines Corporation

InventorsDavid Robert Engebretsen, Steven Lee Gregor, Mayan Moudgill, John Christopher Willis

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Abstract

A processor includes an alias unit having high-speed memory storage locations allocated at compile time for variable-sized data objects. The storage locations are accessed through a table of alias entries that consist of a base address in the processor memory to which the alias entry is aliased, the number of bytes in the alias entry, and a base address that points to the first byte of alias buffer memory representing the value of the alias entry. Each alias entry is given a unique name from a small name space that is encoded into relevant machine opcodes. The names are used to reference the data objects. The processor can optionally include a data cache and can be used in either single processor or multi-tasking environments. Reference to a memory location address associated with an alias register entry would be redirected to the intermediate storage.

Claims37

Dependent claims

A processor system comprising:

a processor core having circuitry that implements processor execution logic and supports instruction set architecture operation;
a memory unit having addressable storage locations in which the processor core stores data objects and from which the processor core retrieves data objects;
and
an alias unit having an alias buffer memory with a plurality of storage locations, a table of alias entries that are indexed by an alias entry name and contain a memory unit address, a length value, and a base address pointer that identifies a storage location in the alias buffer memory, and control logic that reediness a machine instruction from the processor core for allocating storage locations in the alias buffer memory and in response enters a base address value contained in the machine instruction into an alias entry name contained in the machine instruction;
wherein the control logic responds to a compiler-generated instruction to allocate and initialize an alias entry by storing a memory unit address storage location, byte length value, and alias buffer memory base address at an alias entry table index specified in the instruction at compiling run time and then storing a data record located at a beginning memory unit address storage location specified by the alias entry and continuing for the number of address locations specified in the byte length value into the alias buffer memory beginning at the base address and continuing for the number of address locations specified in the byte length value.

2 more elements

A processor comprising:

a load/store unit that receives a machine instruction that specifies requested processor operations for execution;
a plurality of addressable hardware registers;
a memory unit having addressable storage locations in which data objects are stored and from which the data objects are retrieved;
an alias buffer memory with a plurality of storage locations;
a table of alias entries that are indexed by an alias entry name and contain (I) a memory unit address, (ii) a length value, and (iii) a base address pointer that identifies a storage location in the alias buffer memory;
and
alias control logic that receives a compiler-generated instruction from the load/store unit for allocating storage locations in the alias buffer memory and in response enters a base address value contained in the instruction into an alias entry name contained in the instruction;
wherein the alias control logic responds to a received machine instruction to allocate and initialize an alias entry by storing a memory unit address storage location, byte length value, and alias buffer memory base address at an alias entry table index specified in the received instruction at compiling run time and then storing a data record located at a beginning memory unit address storage location specified by the corresponding alias entry and continuing for the number of address locations specified in the byte length value into the alias buffer memory beginning at the base address and continuing for the number of address locations specified in the byte length value specified in the received machine instruction.

5 more elements

A method of performing machine instructions with a processor having circuitry that implements processor execution logic and a memory unit having addressable storage locations in which data objects are stored and from which the data objects are retrieved, the method comprising the steps of:

receiving a compiler-generated instruction for allocating storage locations in an alias buffer memory of the processor that includes a plurality of storage locations;
entering a base address value contained in the machine instruction into a table of alias entries that are indexed by an alias entry name, thereby identifying a group of alias buffer memory locations associated with the alias entry name beginning at the base address value and continuing for a number of buffer memory address locations that are specified in the machine instruction and associated with the alias entry name;
wherein the step of receiving a instruction further comprises responding to a received instruction to allocate and initialize an alias entry by storing a memory unit address storage location, byte length value, and alias buffer memory base address at an alias entry table index specified in the instruction at compiling run time and then storing a data record located at a beginning memory unit address storage location specified by the alias entry and continuing for the number of address locations specified in the byte length value into the alias buffer memory beginning at the base address and continuing for the number of address locations specified in the byte length value.

A computer system comprising:

a processor having
a processor core having circuitry that implements processor execution logic and supports instruction set architecture operation,
a memory unit having addressable storage locations in which the processor core stores data objects and from which the processor core retrieves data objects, and
an alias unit having an alias buffer memory with a plurality of storage locations, a table of alias entries that are indexed by an alias entry name and contain a memory unit address, a length value, and a base address pointer that identifies a storage location in the alias buffer memory, and control logic that receives a compiler-generated instruction from the processor core for allocating storage locations in the alias buffer memory and in response enters a base address value contained in the instruction at compiling run time into an alias entry name contained in the instruction;
an input/output block including one or more devices with which a human operator can control the operation of the processor;
secondary storage in which data is stored and retrieved from;
a data bus over which the processor communicates with the input/output block and secondary storage;
and
a compiler that receives program language code and performs a compile time process to convert it to alias unit instructions prior to executing the converted program language code in a run time process, and allocates variable length blocks of the alias buffer memory prior to run time.

6 more elements

Dependencies are inferred from the claim text.