Memory system with memory presence and type detection using multiplexed memory line function

Abstract

A method and apparatus for enabling the detection of memory presence and identification of memory type in a memory system are disclosed. A memory controller may be connected to a memory bank inserted into a memory bank insertion area, via an interconnect line such as row address strobe (RAS) signal line commonly used to activate or deactivate the memory banks. Presence detect signals are multiplexed over the interconnect line for detecting whether a memory bank is connected to a given line. For connected memory banks, type detection operations may be performed on the interconnect line for detecting the type of memory bank connected thereto. The presence and type detection operations generate output signals to permit the dynamic configuration of a memory system controller. Accordingly, it is possible to implement memory systems capable of accommodating differing quantities and types of memory banks with a single controller utilizing a single interconnect line to enable presence detection and type identification to enable the appropriate configuration thereof. In an embodiment utilizing a select line as the interconnect line, implementation of the presence and type detection is accomplished without the addition of dedicated detect lines to the memory system.

Dependencies are inferred from the claim text.