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US 5,860,128 AGranted
Method and apparatus for sampling data from a memory
AssigneeIntel Corporation
InventorsRobert N. Murdoch, Michael W. Williams, Sathyamurthi Sadhasivan
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AssigneeIntel Corporation
InventorsRobert N. Murdoch, Michael W. Williams, Sathyamurthi Sadhasivan
Estimating the term…
A novel method for performing memory accesses. Falling edges of a column address strobe (CAS) signal are used to cause dynamic random access memories (DRAMs) to drive data corresponding to the current address onto a data bus coupled to the input of a set of latches. A memory latch data (MLAD) signal is used to enable the set of latches. When the MLAD signal is asserted, the latches latch the data at the input in response to a falling edge of the CAS signal. When the MLAD signal is deasserted, the latch does not latch the data at the input in response to the falling edge of the CAS signal. Since the same signal (CAS) is used to control when the data is driven by the DRAMs and when the data is latched by the latches, the differences in output timings, signal path delays, and loads are avoided. The use of expensive timing compensation circuits and special tuning of these circuits for each circuit board redesign is thereby avoided.
A method for accessing a memory comprising the steps of:
A memory controller for accessing a memory, said memory controller producing a first edge of a plurality of edges of a first signal to cause a first data to be driven in response to said first edge of said first signal, and driving a second signal into a first state and producing a second edge of said plurality of edges of said first signal to cause said first data to be latched in response to said second edge of said first signal and said second signal being in said first state.
A computer system comprising:
Dependencies are inferred from the claim text.