US 5,860,127 AGranted

Cache memory employing dynamically controlled data array start timing and a microcomputer using the same

AssigneesHitachi, Ltd., Hitachi ULSI Engineering Corp.

InventorsYasuhisa Shimazaki, Seiichi Nagata, Katuhiro Norisue, Koichiro Ishibashi, Junichi Nishimoto, Shinichi Yoshioka, Susumu Narita

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Abstract

A comparator is constituted such that a hit signal .phi.hit is high, before hit check is established in each way of an address array, and such that the hit signal goes low, when a mishit has been established. When a clock frequency is relatively high, the address array is activated by the first clock signal, and thereafter, all ways of a data array are activated by the second clock signal before the hit check in the address array is established. When the hit check has been established, data read from a way in the data array which has hit is immediately outputted onto a data line and an operation in the way which has mishit is stopped. This novel constitution realizes a high-speed cache operation. When the clock frequency is relatively low, only a way in the data array that has hit is activated after completion of the hit check, thereby reducing power consumption at a low-speed operation.

Claims23

Dependent claims

A cache memory comprising:

a data array for holding a plurality of pieces of data corresponding to a plurality of pieces of data held in another memory;
an address array for holding a plurality of address information associated with pieces of addresses of said another memory for said plurality of pieces of data held in said data array;
a first activating circuit responsive to a read request which requests readout of data from said another memory, for activating said address array to read a piece of address information therefrom associated with a read address specified by said read request;
a hit check circuit for performing hit check on said read address based on the piece of address information read from said address array;
a second activating circuit for activating said data array to read data associated with said read address, said activating being done after said address array is activated;
and
an output control circuit for instructing said data array to output said data associated with said read address and read by activation of said data array, in response to determination as a result of said hit check that said address array has hit;
wherein said second activating circuit has an activation execution circuit for dynamically selecting and executing one of first activating operation for activating said data array after activation of said address array and before completion of said hit check and a second activating operation for activating said data array after said hit check completes and determines that said address array has hit.

5 more elements

A cache memory comprising:

a data array comprises a plurality of data holding ways for holding a plurality of pieces of data, each piece of data being a copy of data held in another memory;
an address array comprises a plurality of address information holding ways each provided in correspondence to one of said plurality of data holding ways, each address information holding way holding a plurality of pieces of address information associated with memory addresses of said another memory for a plurality of pieces of data held in a corresponding one of said plurality of data holding ways;
a first activating circuit responsive to a data read request which requests readout of data from said another memory, for activating said plurality of address information holding ways in parallel, to read a plurality of pieces of address information associated with a memory read address specified by said data read request;
a hit check circuit for executing a hit check on respective ones of said plurality of address information holding ways with respect to said memory read address in parallel, based on a plurality of pieces of address information read from said plurality of address information holding ways;
a second activating circuit for activating said plurality of data holding ways in parallel, to read a plurality of pieces of data associated with said memory read address therefrom, said activating being done after activation of said plurality of address information holding ways and before completion of the hit check on respective ones of said plurality of address information holding ways;
and
an output control circuit for instructing one of said plurality of data holding ways corresponding to one of said plurality of address information holding ways to output data read by the one corresponding data holding has, in response to determination by said hit check that said one address information holding way was hit.

4 more elements

A cache memory comprising:

a data array for holding a plurality of pieces of data corresponding to a plurality of pieces of data in another memory;
an address array for holding a plurality of pieces of address information associated with addresses of said another memory for said plurality of pieces of data held in said data array;
a first activating circuit responsive to combination of a data read request which requests readout of data from said another memory and a first clock signal which controls an operation of said cache memory, for activating said address array to read a piece of address information associated with a read address specified by said data read request;
a hit check circuit for executing hit check on said piece of address information read from said address array with respect to said read address;
a second activating circuit responsive to a second clock signal having the same clock frequency as that of said first clock signal and delayed behind said first clock signal by a predetermined phase difference, for activating said data array after activation of said address array, to read data associated with said read address;
and
an output control circuit responsive to determination by said hit check that said address array has hit, for instructing said data array to output data read by the activating of said data array.

4 more elements

A microprocessor comprising:

a central processing unit;
a cache memory connected to said central processing unit, said cache memory comprising:
a data array for holding a plurality of pieces of data corresponding to a plurality of pieces of data held in another memory;
an address array for holding a plurality of pieces of address information associated with addresses of said another memory for said plurality of pieces of data held in said data array;
a first activating circuit responsive to a read request which requests readout of data from said another memory, for activating said address array to read a piece of address information therefrom associated with a read address specified by said read request,
a hit check circuit for performing hit check on said read address based on the piece of address information read from said address array;
a second activating circuit for activating said data array to read data associated with said read address, said activating being done after said address array is activated;
and
an output control circuit for instructing said data array to output said data associated with said read address and read by activation of said data array, in response to determination as a result of said hit check that said address array has hit;
wherein said second activating circuit has an activation execution circuit for dynamically selecting and executing one of a first activating operation for activating said data array after activation of said address array and before completion of said hit check and a second activating operation for activating said data array after said hit check completes and determines that said address array has hit;
and
a clock supply circuit for supplying a plurality of clock signals for controlling operations of said central processing unit and said cache memory to said cache memory;
wherein said central processing unit, said cache memory, and said clock supply circuit are provided on a common integrated circuit substrate.

10 more elements

A microprocessor comprising:

a central processing unit;
a cache memory connected to said central processing unit, said cache memory comprising:
a data array comprises a plurality of data holding ways for holding a plurality of pieces of data, each piece of data being a copy of data held in another memory;
an address array comprises a plurality of address information holding ways each provided in correspondence to one of said plurality of data holding ways, each address information holding way holding a plurality of pieces of address information associated with memory addresses of said another memory for a plurality of pieces of data held in a corresponding one of said plurality of data holding ways;
a first activating circuit responsive to a data read request which requests readout of data from said another memory, for activating said plurality of address information holding ways in parallel, to read a plurality of pieces of address information associated with a memory read address specified by said data read request;
a hit check circuit for executing hit check on respective ones of said plurality of address information holding ways with respect to said memory read address in parallel, based on a plurality of pieces of address information read from said plurality of address information holding ways;
a second activating circuit for activating said plurality of data holding ways in parallel to read a plurality of pieces of data associated with said memory read address therefrom, said activating being done after activation of said plurality of address information holding ways and before completion of the hit check;
and
an output control circuit for instructing one of said plurality of data holding ways corresponding to one of said plurality of address information holding ways to output data read by the one corresponding data holding way, in response to determination by said hit check that, said one address information holding way has hit;
and
a clock supply circuit for supplying a plurality of clock signals for controlling operations of said central processing unit and said cache memory to said cache memory;
wherein said central processing unit, said cache memory, and said clock supply circuit are provided on a common integrated circuit substrate.

9 more elements

Dependencies are inferred from the claim text.