Controlling shared memory access ordering in a multi-processing system using an acquire/release consistency model

In a computer system, a method of utilizing a set of two instructions to maintain an ordering of an access to a shared location, such that accesses referencing and acquire address and a release address associated with acquiring and releasing said shared location is observed in a program order with said access to said shared location, comprising the steps of:

• implementing a memory in which at least a portion of said memory can be allocated as said shared location;
• implementing a memory accessing device which responds to an execution of a first instruction that specifies said acquire address, wherein said first instruction causes all previous accesses referencing only said acquire address prior to said first instruction to become visible prior to allowing memory accesses following said first instruction;
• implementing said memory accessing device which responds to an execution of a second instruction that specifies said release address, wherein said second instruction causes all previous accesses prior to said second instruction to become visible prior to allowing accesses referencing said release address following said second instruction.

In a computer system, a method of utilizing a set of two instructions to maintain an ordering of an access to a shared location, such that accesses referencing an address associated with said shared location is observed in a program order with said access to said shared location, comprising the steps of:

• implementing a memory in which at least a portion of said memory can be allocated as a shared memory, wherein at least one location within said shared memory is defined as said shared location;
• implementing a processing device which responds to execute a first instruction which specifies said address for acquiring said shared location, wherein said first instruction causes all previous accesses referencing only said address prior to said first instruction to become visible prior to allowing memory accesses following said first instruction;
• implementing said processing device which responds to execute a second instruction which specifies said address for releasing said shared location wherein said second instruction causes all previous accesses prior to said second instruction to become visible prior to allowing accesses referencing said address following said second instruction.

In a computer system having a plurality of processors, a method of utilizing a set of two instructions to maintain an ordering of an access to a shared location in memory accessed by more than one of said processors, such that accesses referencing an acquire address and a release address associated with acquiring and releasing said shared location in memory is observed in a program order with said access to said shared location, comprising the steps of:

• executing a first instruction which specifies said acquire address wherein said first instruction causes all previous accesses referencing only said acquire address prior to said first instruction to become visible prior to allowing memory accesses following said first instruction;
• executing an instruction for accessing said shared location;
• executing a second instruction which specifies said release address wherein said second instruction causes all previous accesses prior to said second instruction to become visible prior to allowing accesses referencing said release address following said second instruction.