Integrated circuit including a real time clock, configuration RAM, and memory controller in a core section which receives an asynchronous partial reset and an asynchronous master reset

An integrated circuit comprising:

• a section of an integrated circuit comprising a core section, wherein said core section includes a plurality of subsystems, wherein three of said plurality of subsystems are:
• a real time clock register, a configuration RAM and a system DRAM memory controller;
• a master reset pin configured upon the integrated circuit, wherein said real time clock register and said configuration RAM are initialized upon receipt of a master reset signal upon the master reset pin;
• and
• a partial reset pin configured upon the integrated circuit, wherein said real time clock register and said configuration RAM are not initialized upon receipt of a partial reset signal upon the partial reset pin;
• wherein said integrated circuit is configured to be coupled to an array of memory cells addressable by said system DRAM memory controller;
• and
• wherein one of said plurality of subsystems includes a configuration register which stores a binary value whereupon receipt of said partial reset signal will reset said DRAM memory controller and inhibit a refresh of said array of memory cells.

An integrated circuit comprising:

• a section of an integrated circuit comprising a core section, wherein said core section includes a plurality of subsystems, wherein three of said plurality of subsystems are:
• a real time clock register, a configuration RAM and a system DRAM memory controller;
• a master reset pin configured upon the integrated circuit, wherein said real time clock register and said configuration RAM are initialized upon receipt of a master reset signal upon the master reset pin;
• and
• a partial reset pin configured upon the integrated circuit, wherein said real time clock register and said configuration RAM are not initialized upon receipt of a partial reset signal upon the partial reset pin;
• wherein said integrated circuit is configured to be coupled to an array of memory cells addressable by said system DRAM memory controller;
• and
• wherein one of said plurality of subsystems includes a configuration register which stores a binary value whereupon receipt of said partial reset signal will not reset said DRAM memory controller and will not inhibit a refresh of said array of memory cells.

A personal information device comprising:

• a reset unit adapted during use for producing a partial reset signal and a master reset signal;
• a subsystem within a core section of an integrated circuit, said subsystem is coupled to receive said partial reset signal and said master reset signal;
• an array of memory cells of a system DRAM coupled to said core section;
• and
• a configuration register within said subsystem, said configuration register having a bit location determinative of whether said array of memory cells are to receive refresh while said partial reset is active and further having a bit location determinative of one of a CAS before RAS refresh mode for said array of memory cells of said system DRAM or a self refresh mode for said array of memory cells of said system DRAM.

An integrated circuit comprising:

• a section of an integrated circuit comprising a core section, wherein said core section includes:
• a real time clock register, a configuration RAM and a system DRAM memory controller;
• a master reset pin configured upon the integrated circuit, wherein said real time clock register, said configuration RAM, and said system DRAM memory controller are initialized upon receipt of a master reset signal upon the master reset pin;
• and
• a partial reset pin configured upon the integrated circuit, wherein said real time clock register and said configuration RAM are not initialized upon receipt of a partial reset signal upon the partial reset pin, and wherein said system DRAM memory controller is programmable to provide or not provide refresh to an array of memory cells upon receipt of a partial reset signal upon the partial reset pin.