US 5,860,120 A · Directory-based coherency system using two bits to maintain coherency on a dual ported memory system

Abstract

An improved directory-based cache coherency memory system for a multiprocessor computer system. The memory system includes a dual ported system memory shared by the multiple processors within the computer system; a plurality of data cache memories, at least one data cache memory associated with each processor; and first and second memory busses, the first memory bus connecting a first subset of processors and associated data cache memories to a first port (PORT A) of the system memory, and the second memory bus connecting a second subset of processors and associated data cache memories to a second port (PORT B) of the system memory. Cache coherency is maintained through the use of memory line state information saved with each line of memory within the system memory and data cache memories. The system memory contains a system memory line state for each line of memory saved within the system memory, the system memory line state being any one of the group: SHARED PORT A, SHARED BOTH, OWNED PORT A and OWNED PORT B. Each one of these states is represented by a different two bit code saved with each line of memory in system memory. Additionally, each data cache memory contains a data cache memory line state for each line of memory saved within the data cache memory, the data cache memory line state being any one of the group: MODIFIED, EXCLUSIVE, SHARED, or INVALID.

Claims6

Dependent claims

A method for maintaining cache coherency within a computer system including multiple processors, a data cache memory associated with each processor, a system memory shared by said multiple processors, and first and second memory busses, said first memory bus connecting a first subset of said multiple processors and associated data cache memories to a first port (PORT A) of said system memory, and said second memory bus connecting a second subset of said multiple processors and associated data cache memories to a second port (PORT B) of said system memory;

said method comprising the steps of:
storing a data cache memory line state with each line of memory saved within said data cache memories, said data cache memory line state being any one of the group:
MODIFIED, EXCLUSIVE, SHARED, or INVALID;
storing a system memory line state with each line of memory saved within said system memory, said system memory line state being any one of the group:
SHARED PORT A, SHARED BOTH, OWNED PORT A and OWNED PORT B;
reading the system memory line state for a line of memory to determine the location of the most current copy of said line of memory within said system memory and data cache memories during a memory I/O operation requiring the most current copy of said line of memory;
and
changing the system memory line state for said line of memory and the data cache memory line state for each copy of said line of memory contained in said data cache memories to identify the location of the most current copy of said line of memory within said system memory and data cache memories following a memory I/O operation which updates said line of memory.

5 more elements

A directory-based cache coherency memory system for a computer system including multiple processors, the memory system comprising:

a system memory shared by said multiple processors, said system memory containing a system memory line state for each line of memory saved within said system memory, said system memory line state being any one of the group:
SHARED PORT A, SHARED BOTH, OWNED PORT A and OWNED PORT B;
a plurality of data cache memories, at least one data cache memory associated with each one of said processors, each one of said data cache memories containing a data cache memory line state for each line of memory saved within said data cache memories, said data cache memory line state being any one of the group:
MODIFIED, EXCLUSIVE, SHARED, or INVALID;
and
first and second memory busses, said first memory bus connecting a first subset of said multiple processors and associated data cache memories to a first port (PORT A) of said system memory, and said second memory bus connecting a second subset of said multiple processors and associated data cache memories to a second port (PORT B) of said system memory.

3 more elements

Dependencies are inferred from the claim text.

Directory-based coherency system using two bits to maintain coherency on a dual ported memory system

Life of this patent

Directory-based coherency system using two bits to maintain coherency on a dual ported memory system

Life of this patent

Abstract

Claims6