Method and apparatus for managing snoop requests using snoop advisory cells

A method for managing snoop requests to a processor structure which accesses data in a memory structure external to said processor structure, said memory structure having a first address space and said processor structure including a cache memory for caching data of said first address space for said processor structure, for use with an additional device which also accesses data in said first address space of said memory structure, and for use further with a first snoop advisory cell, comprising the steps of:

• in response to each read access by said processor structure, determining if said read access is to an address which is within a first subset of addresses in said first address space, and if said read access is of a predetermined type, writing a "snoop yes" value into said first snoop advisory cell;
• in response to each particular access by said additional device to an address which is within said first subset of addresses in said first address space, issuing a snoop request to said processor structure for the address of said particular access if said first snoop advisory cell contains said "snoop yes" value, and if said first snoop advisory cell does not contain said "snoop yes" value, accessing said memory structure without issuing said snoop request;
• and
• recurrently performing the following steps in conjunction with each other:
• causing said processor structure to synchronize with said memory structure all data of said first subset of addresses which is cached in said cache memory, and
• writing a "snoop no" value into said first snoop advisory cell.

A method for managing snoop requests to a processor structure which accesses data in a memory structure external to said processor structure, said memory structure having a first address space and said processor structure including a cache memory for caching data of said first address space for said processor structure, for use with an additional device which also accesses data in said first address space of said memory structure, and for use further with a plurality of snoop advisory cells, each corresponding to a respective distinct subset of said first address space, comprising the steps of:

• response to a first read access by said processor structure, determining
• if said first read access is a first address which is within a first subset of addresses in said first address space, and if said first read access is of a predetermined type, writing a "snoop yes" value into the a first snoop advisory cell corresponding to said first subset of addresses;
• in response to a second access by said additional device, determining if said second access is to a second address which is within a second subset of addresses in said first address space, and issuing a snoop request to said processor structure for said second address if a second snoop advisory cell corresponding to said second subset contains said "snoop yes" value, and if said second snoop advisory cell does not contain said "snoop yes" value, accessing said memory structure without issuing said snoop request;
• and
• recurrently performing the following steps in conjunction with each other:
• causing said processor structure to synchronize with said memory structure all data of each of said subsets of addresses which is cached in said cache memory, and
• writing "snoop no" values into each of said snoop advisory cells.

Snoop request management apparatus, for use with a memory structure and a processor structure which accesses data in said memory structure, said memory structure having a first address space and said processor structure including a cache memory for caching data of said first address space for said processor structure, for use with an additional device which also accesses data in said first address space of said memory structure, comprising:

• a first snoop advisory cell;
• processor monitoring circuitry coupled to said processor structure and to said first snoop advisory cell, said processor monitoring circuitry, in response to each given read access by said processor structure, determining if said given read access is to an address which is within a first subset of addresses in said first address space, and if said given read access is of a predetermined type, writing a "snoop yes" value into said first snoop advisory cell;
• clearing circuitry coupled to said first snoop advisory cell, said clearing circuitry writing a "snoop no" value into said first snoop advisory cell at predetermined times;
• and
• snoop decision circuitry coupled to said first snoop advisory cell and further coupled to detect accesses by said additional device, said snoop decision circuitry having a snoop decision output and, in response to each particular access by said additional device to an address which is within said first subset of addresses in said first address space, asserting a "snoop necessary" value on said snoop decision output if said first snoop advisory cell contains said "snoop yes" value and asserting a "snoop unnecessary" value on said snoop decision output if said first snoop advisory cell does not contain said "snoop yes" value.

Snoop request management apparatus, for use with a memory structure and a processor structure which accesses data in said memory structure, said memory structure having a first address space and said processor structure including a cache memory for caching data of said first address space for said processor structure, said cache memory having a plurality of entries, for use with an additional device which also accesses data in said first address space of said memory structure, comprising:

• a plurality of snoop advisory cells, each corresponding to a respective distinct subset of addresses in said first address space;
• setting circuitry coupled to said snoop advisory cells and further coupled to detect a first read access indicating, according to a first predetermined test, that at least one of said cache memory entries may now be mapped to an address which is within a first subset of addresses said setting circuitry writing a "snoop yes" value into a first snoop advisory cell corresponding to said first subset of addresses in response to the first read access;
• clearing circuitry coupled to said snoop advisory cells, and further coupled to detect a second occurrence indicating, according to a second predetermined test, that none of said cache memory entries remain mapped to an address which is within a second subset of addresses, said clearing circuitry writing a "snoop no" value into a second snoop advisory cell corresponding to said second subset of addresses in response to said second occurrences;
• and
• snoop decision circuitry coupled to said snoop advisory cells and further coupled to detect accesses by said additional device, said snoop decision circuitry having a snoop decision output and, in response to a third access by said additional device to a third address which is within a third subset in said first address space, asserting a "snoop advised" value on said snoop decision output if a third snoop advisory cell corresponding to said third subset of addresses contains said "snoop yes" value and asserting a "snoop unnecessary" value on said snoop decision output if said third snoop advisory cell does not contain said "snoop yes" value.