Method and apparatus for blending bus writes and cache write-backs to memory

A buffer for combining data comprising:

• a plurality of buffer entries, wherein each buffer entry may be written to in an increment that is less than a data storage capacity of each buffer entry;
• a local bus write buffer that stores data from a local bus master;
• a first circuit that selects data items provided by a cache and a bus master;
• and
• a second circuit that writes a first selected data item from the cache to at least one available increment of a buffer entry, a second selected data item from the bus master being written to at least one increment of the buffer entry containing data from the cache, wherein the second circuit comprises a second multiplexer having inputs coupled to select valid data provided by either the cache or the bus master or to select data presently stored in the buffer entry.

A circuit for combining and storing data comprising:

• a local bus write buffer that stores data from a local bus master,
• a common write buffer having a plurality of buffer entries wherein each buffer entry may be written to in an increment that is less than a data storage capacity of each buffer entry,
• a first circuit that selects data items from either a cache or a local bus write buffer for writing to the common write buffer, and
• a second circuit that writes a first valid data item selected from the cache to a buffer entry of the common write buffer at positions at which no valid data from a bus master is stored, the second circuit writing a second valid data item selected from the local bus write buffer to positions in the buffer entry, wherein the second circuit comprises a second multiplexer having inputs coupled to select valid data provided by either the cache or the bus master or to select data presently stored in a common write buffer entry.

A computer system comprising a bridge circuit coupled among a central processing unit (CPU) and a memory and a bus, the bridge circuit comprising:

• a local bus write buffer that stores data from a bus master,
• a common write buffer having a plurality of buffer entries wherein each buffer entry may be written to in an increment that is less than a data storage capacity of each buffer entry,
• a first circuit that selects data items from a processor and a local bus write buffer for writing to the common write buffer, and
• a second circuit that writes a first valid data item selected from the processor to the common write buffer at positions at which no valid data from the local bus write buffer is stored, the second circuit writing a second valid data item selected from the local bus write buffer to any position of the common write buffer, wherein the second circuit comprises a second multiplexor having inputs coupled to select valid data provided by either the processor or the bus master or to select data presently stored in a common write buffer entry.