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AssigneeNational Semiconductor Corporation
InventorsMarvin Wayne Martinez, Jr., Mark Bluhm, Jeffrey S. Byrne, David A. Courtright, Douglas Ewing Duschatko, Raul A. Garibay, Jr., Margaret R. Herubin
Estimating the term…
A write-back coherency system is used, in an exemplary embodiment, to implement write-back caching in an x86 processor installed in a multi-master computer system that does not support a write-back protocol for maintaining coherency between an internal cache and main memory during DMA operations. The write-back coherency system interrupts the normal bus arbitration operation to allow export of dirty data. In response to an arbitration-request (such as HOLD), if the internal cache contains dirty data, the processor is inhibited from providing arbitration-acknowledge (such as HLDA) until the dirty data is exported (the cache is dynamically switched to write-through mode to prevent data in the cache from being made dirty while the bus is arbitrated away). While the requesting bus master is accessing memory, bus snooping is performed and invalidation logic invalidates at least those cache locations corresponding to locations in memory that are affected by the requesting bus master.
In a multi-master computer system including an x86 processor with an internal cache, where the computer system does not support operating the processor in write-back mode by implementing a write-back coherency protocol to maintain coherency between the internal cache and main memory during DMA (direct memory access) operations, a write-back coherency system to support use of a processor in which the internal cache is operable in write-back mode or write-through mode, comprising:
In a multi-master computer system including an x86 processor with an internal cache, where the computer system does not support operating the processor in write-back mode by implementing a write-back coherency protocol to maintain coherency between the internal cache and main memory during DMA (direct memory access) operations, a write-back coherency system to support use of a processor in which the internal cache is operable in write-back mode or write-through mode, comprising:
A write-back coherency method for use in a multi-master computer system including an x86 processor with an internal cache, where the computer system does not support operating the processor in write-back mode by implementing a write-back coherency protocol to maintain coherency between the internal cache and main memory during DMA (direct memory access) operations, the write-back coherency method supporting use of a processor in which the internal cache is operable in write-back mode or write-through mode, comprising:
Dependencies are inferred from the claim text.