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AssigneeCanon Kabushiki Kaisha
InventorsToshiyuki Fukui, Kazumasa Hamaguchi, Shuichi Nakamura
Estimating the term…
When a synchronization point is determined to maintain the coherence of data in a multi-processor system, and data write-back operations from caches to a main memory are simultaneously performed at the determined point, the traffic is concentrated, resulting in poor efficiency. In view of this problem, the write-back operations of cache data are arbitrarily performed when a predetermined condition is satisfied. Alternatively, when the number of copies which are updated in the cache and do not match the corresponding data in the main memory exceeds a predetermined value, cache data are written back. With this control, the write-back operations of copies stored in cache can be prevented from being concentrated at the synchronization point.
An information processing system adopting a relaxed memory coherence model, the system includes a plurality of connection network use subjects each including a plurality of processor units, cache memory units connected to said plurality of processor units, and a main memory unit, and a connection network for interconnecting said plurality of connection network use subjects, and executes coherence maintenance processing for maintaining coherence of contents of a data block stored in each cache memory unit connected to each processor unit when processing of each of said plurality of processor units has reached a predetermined synchronization point,
Dependencies are inferred from the claim text.