Method and clustered multi-processor system for controlling a clock phase for clusters
AssigneeNEC Corporation
InventorKoichi Horikawa
Life of this patent
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Abstract
In a clustered multi-processor system and method, first and second clusters are connected between first and second directories. The first directory checks whether an address of a request on a first system bus coincides with an address of a request from the second directory. When the first directory detects the coincidence, the first directory cancels the request on the first system bus, and reissues the request. Since the first system bus and a second system bus have a different clock phase, the requests are checked without overlapping.
Claims21
A multi-processor system having a plurality of clusters including at least one processor, at least one cache memory, a shared memory, and a system bus for connecting said at least one cache memory and said shared memory, said multi-processor system comprising:
- a synchronization controller for shifting clocks of clusters of said plurality of clusters in relation to one another such that the clock of a first cluster of said plurality of clusters is separated in time from a clock of a second cluster of said plurality of clusters;
- and
- a directory for transferring requests and data among said clusters of said plurality of clusters,
- wherein said synchronization controller includes:
- a delay circuit for delaying a signal associated with said system bus to produce a delayed signal;
- and
- a selector for selecting one of the signal associated with said system bus and the delayed signal from said delay circuit.
A multi-processor system having a plurality of clusters, each of said clusters comprising:
- at least one processor;
- at least one cache memory connected to said at least one processor;
- a shared memory coupled to said at least one cache memory;
- a first system bus for connecting said at least one cache memory and said shared memory;
- a directory for transferring requests and data among other clusters of said plurality of clusters;
- and
- a synchronization controller for shifting a clock of said first system bus in relation to a clock of a second system bus in a second cluster of said plurality of clusters such that the clock of said first system bus is generated in time from the clock of said second system bus,
- wherein said synchronization controller includes:
- a delay circuit for delaying a signal associated with said first system bus to produce a delayed signal;
- and
- a selector for selecting one of the signal associated with said first system bus and the delayed signal from said delay circuit.
A method of controlling a multiprocessor system having a plurality of clusters, each of said clusters including at least one processor, at least one cache memory coupled to said at least one processor, a shared memory, and a system bus for connecting said at least one cache memory and said shared memory, said method comprising:
- shifting a clock of respective clusters of said plurality of clusters in relation to one another such that respective clocks of said respective clusters are generated in time;
- and
- detecting whether a first address of a first request from a first cluster is coincident with a second address of a second request from a second cluster,
- wherein said step of shifting includes:
- delaying a signal associated with said system bus to produce a delayed signal;
- and
- selecting one of the signal associated with said system bus and the delayed signal.
Dependencies are inferred from the claim text.