Processor and method for store gathering through merged store operations
AssigneesInternational Business Machines Corporation, Motorola, Inc.
InventorRajesh Bhikhubhai Patel
Life of this patent
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Abstract
First and second store instructions that target one or more locations in a cache memory are identified. A determination is made whether the cache memory is busy. In response to a determination that the cache memory is busy, the operations specified by the first and second store instructions are merged into a single store operation that subsumes store operations specified by the first and second store instructions. Thereafter, the single store operation is performed.
Claims25
A method of store gathering within a processor having a cache memory associated therewith, said processor further coupled to a bus, said method comprising:
- identifying first and second store instructions that target one or more locations in said cache memory;
- determining if performing an operation indicated by said first store instruction entails communication via said bus;
- determining whether said cache memory is busy;
- in response to a determination that performing said operation indicated by said first store instruction entails communication via said bus, merging said first and second store instructions into a single store operation regardless of whether said cache memory is busy;
- in response to a determination that performing said operation indicated by said first store instruction does not entail communication via said bus and a determination that said cache memory is busy, merging said first and second store instructions into a single store operation;
- and
- thereafter, performing said single operation.
a processor having a cache memory associated therewith, said processor comprising:
- a bus interface unit coupling the processor to a bus;
- execution control logic for identifying first and second store instructions that target one or more locations in said cache memory;
- merging logic coupled to said execution control logic, wherein said merging logic merges said first and said second store instructions into a single store operation in response to a determination that said cache memory is busy and a determination that performing an operation indicated by said first store instruction does not entail communication via said bus;
- said merging logic merges said first and second store instructions into a single store operation regardless of whether said cache memory is busy in response to a determination that performing said operation indicated by said first store instruction entails communication via said bus;
- and
- memory access logic coupled to said merging logic, wherein said memory access logic perform said single store operation.
A data processing system comprising:
- a cache memory;
- a bus;
- a processor coupled to said cache memory and said bus, said processor including:
- execution control logic for identifying first and second store instructions that target one or more locations in said cache memory;
- merging logic coupled to said execution control logic, wherein said merging logic merges said first and said second store instructions into a single store operation in response to a determination that said cache memory is busy and a determination that performing an operation indicated by said first store instruction does not entail communication via said bus;
- said merging logic merges said first and second store instructions into a single store operation regardless of whether said cache memory is busy in response to a determination that performing said operation indicated by said first store instruction entails communication via said bus;
- and
- memory access logic coupled to said merging logic, wherein said memory access logic perform said single store operation.
Dependencies are inferred from the claim text.