Method and apparatus for dynamically adjusting power/performance characteristics of a memory subsystem

A computer system comprising:

• a processor;
• a memory system;
• at least one bus;
• means for tracking behavior of a memory subsystem;
• means for predicting the occurrence of an event in the memory subsystem based on the tracked behavior;
• and
• means for dynamically adjusting a mode of operation of the memory subsystem responsive to the predicting means wherein the means for dynamically adjusting enables a tag array if the probability of the event reaches a first predetermined level, enables a data cache if the probability of the event reaches a second predetermined level, and only enables the data cache if the event actually occurs if the probability of the event has not reached the second predetermined level.

A method of dynamically adjusting characteristics of a computer system having a processor coupled to a memory subsystem including a cache, comprising the steps of:

• recording information of prior activity of the memory subsystem;
• predicting a probability of a cache hit on a next transaction with the cache;
• enabling a tag array if the probability of a cache hit reaches a predetermined level;
• enabling a data cache if the hit probability reaches a second predetermined level;
• and
• enabling the data cache only if a hit actually occurs if the hit probability has not reached the second predetermined level.