Cache memory circuit

#1. Field of the Invention

#This invention relates to the field of data processing. More particularly, this invention relates to cache memory circuits of the type that are typically used to provide short term, high speed storage for instruction words or data words.

#2. Description of the Prior Art

#FIG. 1 schematically illustrates a data processing system incorporating a cache memory circuit;

#FIG. 2 illustrates the steps of the operation of the cache memory circuit of FIG. 1 when operating in a write back mode;

#FIG. 3 illustrates the read and write operations in accordance with FIG. 2;

#FIG. 4 illustrates an integrated circuit 34 incorporating a central processing unit core 36, a cache memory circuit 38, a write buffer 40 and a multiplexer 42. A random access memory 44 is coupled to the various components of the integrated circuit 34 via the multiplexer 42.

#FIG. 5 illustrates the steps in the operation of the system of FIG. 4 when replacing a cache row. At step 46 a cache miss is detected. At step 48 the cache row to be replaced is identified in accordance with one of the known row replacement strategies. At step 50, the old word from the first location (W#0, in this case the specified word that resulted in the cache miss) is read from the cache memory circuit 38 via a read bus and stored within the write buffer 40. This operation takes one fast clock cycle (fclk) of the integrated circuit 32.

#At step 52 the integrated circuit 32 changes its clock signal to synchronize with the clock signal of the random access memory 44 (mclk).