Loading patent…
AssigneeInternational Business Machines Corporation
InventorsKurt Alan Feiste, Thomas J. Somyak
Estimating the term…
A L2 (high-level) cache according to the present invention implements an efficient pipelined algorithm for flushing the high-level cache and back-invalidating a L1 (low-level) cache. Initially, an address calculation stage calculates the address of a directory entry contained in an array of directory entries every clock cycle. Connected to this address calculation stage is a directory entry lookup stage. The directory entry lookup stage receives an address from the address calculation stage and retrieves the directory entry to be modified from the array of directory entries. Finally, a directory entry modification stage, connected to the directory entry lookup stage, receives the directory entry from the directory entry lookup stage. The directory entry modification stage first looks to see if the directory entry is not marked as invalid. If the directory entry is already marked as invalid, no further processing need be performed on the directory entry. If the directory entry modification stage determines the directory entry to not be invalid, the directory entry modification stage invalidates the directory entry to create a invalid directory entry. Next, the directory entry modification stage stores the invalid directory entry in the array of directory entries. The address calculation stage, the directory entry lookup stage, and the directory entry modification stage within the high-level cache can each perform a new operation every clock cycle. Also connected to the directory entry lookup stage is a castout stage. The castout stage receives a directory entry from the directory entry lookup stage and sends a flush signal to the processor. The flush signal directs the processor to invalidate a line in the low-level cache which corresponds to the directory entry. Also, the castout stage writes the modified contents of the high-level cache to memory.
A data processing system including a high-level cache containing a pipelined flushing apparatus for efficiently flushing the high-level cache and back invalidating a low-level cache, comprising:
A method in a data processing system which includes a high-level cache containing a pipelined flushing apparatus for efficiently flushing the high-level cache and back invalidating a low-level cache, comprising:
Dependencies are inferred from the claim text.
Drawings are temporarily unavailable. Open the PDF at USPTO
No related US applications are recorded in the indexed filing history.
Multiuser, multiprocessor or multiprocessing cache systems: with multilevel cache hierarchies
Computing and data processing
Term ended 7 Oct 2016 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
1. Technical Field
The present invention relates generally to cache units contained within a data processing system. More specifically, the present invention relates to improving the coordination of operations between different level caches.
2. Description of the Related Art
The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself however, as well as a preferred mode of use, further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
FIG. 1 illustrates a block diagram of a multiprocessor data processing system;
FIG. 2 depicts a direct mapped L2 cache according to the present invention;
FIG. 1 illustrates a block diagram of a two-processor data processing system according to the present invention. Data processing system 100 contains processor 102 and low-level cache 104 (hereinafter referred to as L1 cache 104), which are attached to high-level cache 106 (hereinafter referred to L2 cache 106). In one embodiment, processor 102 and L1 cache 104 are integral, but this is not required for the present invention. L1 cache 104 contains a cache controller and cache RAM. L2 cache 106 is comprised of a cache controller and cache RAM.
L2 cache 106 is connected to L1 cache 104 and system bus 114, and functions according to the present invention. One feature of L2 cache 106 is that it will respond to requests snooped from system bus 114 differently, depending upon whether a line's MESI state is Invalid or Modified, when the line's L1 Inclusive bit is set (hereinafter referred to as the Invalid or Modified/L1 Inclusive state). If a line in L2 cache 106 is in the Invalid/L1 Inclusive state, L2 cache 106 will continue to snoop system bus 114 for requests which would affect that line with the knowledge that its copy of the line is invalid, but the copy of the line in L1 cache 104 may be valid. Likewise, when a line in L2 cache 106 is in a Modified/L1 Inclusive state, L2 cache 106 will snoop for requests which would affect the line, knowing that the data stored in the line is valid, but that L1 cache 104 may contain a more recent version of the data for that particular line.
Processor 108, L1 cache 110, and L2 cache 112 can operate in a manner similar to processor 102, L1 cache 104 and L2 cache 106. In the alternative, processor 108, L1 cache 110, and L2 cache 112 may operate as prior art devices, with L2 cache 112 not employing the present invention. Further, these devices need not be present in data processing system 100. L2 cache 106 increases the performance of data processing system 100 regardless of whether processor 102 is the only processor in data processing system 100.