Conflict cache having cache miscounters for a computer memory system

A cache system in a computer comprising:

• a higher cache;
• a lower cache, the higher cache and the lower cache part of a memory hierarchy in which the higher cache is higher in the memory hierarchy than the lower cache;
• the higher cache and the lower cache each containing a copy of a conflict data item;
• a conflict cache electronically coupled to the lower cache and adapted to store the conflict data item when a conflict miss in the lower cache results in eviction of the conflict data item;
• and
• wherein when a conflict miss results in an eviction of the conflict data item from the lower cache to the conflict cache, the conflict data item is not evicted from the higher cache.

A method for reducing cache misses in a cache memory system, the method comprising the following steps:

• receiving, by a first cache and by a conflict cache, from a processor, a request for a data item;
• incrementing a counter, by the conflict cache, only when the data item has an address within a particular logical memory bin and the request for the data item results in a cache miss in the first cache and in a cache hit in the conflict cache;
• and
• remapping a page within the particular logical memory bin, by an operating system, when the counter exceeds a predetermined value.

A method of inclusion for a computer cache system, comprising the following steps:

• receiving, by a lower cache and by a higher cache, the higher cache higher in a memory hierarchy than the lower cache, from a processor, a request for a particular data item, the lower cache and the higher cache each containing a copy of a conflict data item that conflicts with the particular data item;
• evicting the conflict data item, by the lower cache, from the lower cache to a conflict cache;
• and
• permitting, by the higher cache, the conflict data item to remain in the higher cache.