Reduced instruction processor/storage controller interface
AssigneeUnisys Corporation
InventorsDonald C. Englin, Mitchell A. Bauman
Life of this patent
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Abstract
Method and apparatus for reducing address/function transfer pins in a system where cache memories in a system controller are accessed by a number of instruction processors. The reduction of pins is obtained by using two data transfers. The increase in data addressing time, which would otherwise occur using two data transfers, is reduced to nearly the time of the data transfers themselves by responding to the first data transfer while the second data transfer is taking place.
Claims12
In a data system including at least one first apparatus having caches and including at least one second apparatus which stores data into and reads data from the first apparatus caches, the improvement comprising:
- a) the first apparatus having tag memory means for storing cache addresses;
- b) means for transmitting address information and function information from the second apparatus to the first apparatus in a data set of two data words, a first data word containing a tag memory address and a first cache address portion, a second data word containing a second cache address portion;
- c) logic means for controlling said tag memory means and the caches by using said first data word to obtain a partial cache address from said tag memory means and to read data from the caches, said logic means comparing said partial cache address with said first cache address portion and said second cache address portion, a match between said partial cache address and said first cache address portion and said second cache address portion confirming the presence of said partial cache address within said caches, said data read from said caches being available when the presence of said partial cache address is confirmed.
A data system comprising:
- a) at least a first apparatus having caches and tag memory apparatus;
- b) at least a second apparatus;
- c) said first and said second apparatus having a transmission apparatus arranged to transfer data words there between arranged such that said second apparatus can store data in and read data from said caches, and such that address and function information can be transmitted from said first apparatus to said second apparatus in a data set of two data words, a first data word containing a tag memory address and a first cache address portion, a second data word containing a second cache address portion;
- d) said first apparatus having a logic apparatus arranged to obtain a partial cache address from said tag memory and to read said data from said caches, and compare said partial cache address with said first cache address portion and said second cache address portion for a match to confirm the presence of said partial cache address within said caches, said data read from said caches being available when the presence of said partial cache address is confirmed.
A method of operating a data system, the method comprising the steps of:
- a) providing at least one first apparatus having caches and a tag memory apparatus;
- b) providing at least one second apparatus;
- c) providing a transmission apparatus arranged to transfer data words between said first apparatus and said second apparatus arranged such that said second apparatus can store data in and read data from said caches, and such that address and function information can be transmitted from said second apparatus to said first apparatus in a data set of two data words, a first data word containing a tag memory address and a first cache address portion, a second data word containing a second cache address portion;
- d) providing a logic apparatus to obtain a partial cache address from said tag memory and to read data from said caches,
- e) transmitting a first data word from said second apparatus to said first apparatus;
- f) reading said partial cache address from said tag memory;
- g) reading said data from said caches;
- and
- h) comparing said partial cache address with said first cache address portion and said second cache address portion for a match to confirm the presence of said partial cache address within said caches, said data read from said caches being available when the presence of said partial cache address is confirmed.
Dependencies are inferred from the claim text.