Apparatus and method for addressing a cache memory in a computer system utilizing cache tag memory with integrated adder and pre-decode circuit
AssigneeLSI Logic Corporation
InventorsDuane G. Breid, Roger Roisen, Ronald D. Isliefson
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Abstract
A tag memory circuit includes an address index input, an address offset input and an integrated adder and pre-decode circuit. The integrated adder and pre-decode circuit has a first addend input coupled to the address index input, a second addend input coupled to the address offset input, and a pre-decoded sum output. A final row decode and word line driver circuit is coupled to the pre-decoded sum output and generates a word line output which is coupled to the address inputs of a tag memory array. The data outputs of the tag memory array are coupled to a sense amplifier.
Claims13
A tag memory circuit for a cache in a computer system, the tag memory circuit comprising:
- a tag memory array comprising a plurality of address inputs and a plurality of data outputs;
- a sense amplifier circuit coupled to the data outputs;
- an address index input and an address offset input;
- an integrated adder and pre-decode circuit comprising a first addend input coupled to the address index input, a second addend input coupled to the address offset input, and a pre-decoded sum output;
- a row decode circuit coupled to the pre-decoded sum output and having a row decode output;
- and
- a word line driver circuit coupled between the row decode output and the plurality of address inputs.
A method of generating a plurality of word lines for a tag memory in a cache system, the method comprising:
- receiving an address index and an address offset;
- adding selected bits of the address index and the address offset together to obtain a sum output;
- decoding the sum output during the step of adding and as an integrated function with the step of adding to obtain a plurality of pre-decoded address signals;
- and
- decoding the pre-decoded address signals to generate the plurality of word lines.
A tag memory circuit for a cache in a computer system, the tag memory circuit comprising:
- a tag memory array having a plurality of address inputs;
- means for receiving an address index and an address offset;
- means for adding together and decoding selected bits of the address index and the address offset as an integrated function to obtain a pre-decoded sum output;
- and
- means for further decoding the pre-decoded sum output to generate a plurality of word lines and applying the word lines to the plurality of address inputs.
Dependencies are inferred from the claim text.