48-bit wide memory architecture addressing scheme reconfigurable for 8-bit, 16-bit and 32-bit data accesses
AssigneeAlliance Semiconductor Corporation
InventorsSpencer H. Greene, Andrew D. Daniel
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Abstract
A memory addressing method and system is disclosed. In a preferred embodiment, a 48-bit wide memory array is provided wherein eight, 32-bit groups of data are addressable at six (6) memory address locations. Six of the eight 32-bit data groups are addressable at the six memory address locations, while the remaining two 32-bit groups are addressable at aligned, memory address pairs. No page break will occur across the memory address pairs. The contents of the memory are accessed through linear and contiguous addressing. No divide by three operation is required.
Claims16
A memory system, comprising:
- a memory having a plurality of storage locations each being accessed at a particular memory address;
- and
- addressing means operable in
- a full use mode for accessing each memory address as an integral addressable unit, and
- a partial use mode for accessing a first portion of each memory address as an integral number of linear addressable units, and accessing a second portion of selected memory addresses as a fraction of selected linear addressable units, multiple second portions of selected memory addresses being addressed to access the selected linear addressable units.
In a computer system that generates a plurality of linear addresses for accessing data in a memory array, the memory array having a plurality of storage locations, each storage location being accessed by a memory address, wherein two of every three storage locations are packed and one of every three storage locations, is partially filled with data, a method of addressing the memory array as a linear and contiguous region of addressable units of a predetermined bit length, comprising the steps of:
- multiplying upper bits of the linear address by 3N where N is an integer, to generate a chunk base memory address;
- and
- generating at least a first three memory addresses and at least a first memory address pair from the chunk base memory address and lower bits of the linear address, each of the first three memory addresses corresponding to three addressable units, the first memory address pair corresponding to a fourth addressable unit.
A memory addressing system, comprising:
- a memory including a plurality of storage locations, each storage location being addressable by a memory address and being M bits wide, where M is a multiple of three;
- a linear address-to-memory address (LA/MA) converter for generating six memory addresses for six of eight linear addresses, and for further generating a memory address pair for the remaining two of the eight linear addresses;
- and
- a memory controller for generating memory control signals for accessing storage locations within said memory, said memory controller generating two consecutive control signals in response to the memory address pair.
Dependencies are inferred from the claim text.