I/O bus expansion system wherein processor checks plurality of possible address until a response from the peripheral selected by address decoder using user input

A processing system for reading at least one data input having a meaning defined by the user which is applied to the processing system, the processing system comprising:

• a peripheral device having at least one device address input, whereby the peripheral device has a plurality of possible device addresses dependent on each device address input;
• the at least one data input coupled to the at least one device address input of the peripheral device, each data input having two states whereby the device address of the peripheral device is at least partially based upon the state of each data input;
• and
• a microprocessor coupled to the peripheral device, the microprocessor configured to attempt communication with the peripheral device by checking the plurality of possible device addresses of the peripheral device until the peripheral device gives a response to the microprocessor, wherein the device address to which the peripheral device responds represents the state of each data input and the state of each data input is interpreted by the microprocessor in accordance with the user-defined meaning of the respective data input.

A method for expanding the input capability of a microprocessor system to read at least one data input having a meaning defined by the user which is applied to the microprocessor system, the microprocessor system including a peripheral device having at least one device address input, the at least one data input coupled to the at least one device address input of the peripheral device, each data input having two states whereby the device address of the peripheral device is at least partially based upon the state of each data input, and a microprocessor coupled to the peripheral device, the method comprising the steps of:

• (a) attempting to communicate with the peripheral device by using one possible device address of the peripheral device;
• (b) repeating step (a) using different possible device addresses of the peripheral device until the peripheral device responds to the microprocessor;
• and
• (c) using the device address to which the peripheral device responds to determine the state of each data input, the state of each data input being interpreted by the microprocessor in accordance with the user-defined meaning of the respective data input.

A processing system for reading at least one data input signal having a meaning defined by the user which is applied to the processing system, each data input signal having at least two states, the processing system comprising:

• a peripheral device having device address input means whereby the peripheral device has a plurality of possible device addresses dependent on the device address input;
• at least one data input means coupled to the device address input means of the peripheral device, the data input means being representative of the data input signal, whereby the device address of the peripheral device is at least partially based upon the state of each data input signal;
• and
• a microprocessor coupled to the peripheral device, the microprocessor configured to attempt communication with the peripheral device by checking the plurality of possible device addresses of the peripheral device until the peripheral device gives a response to the microprocessor, wherein the device address to which the peripheral device responds represents the state of each data input signal and the state of each data input signal is interpreted by the microprocessor in accordance with the user-defined meaning of the respective data input signal.