US 5,860,014 AGranted

Method and apparatus for improved recovery of processor state using history buffer

AssigneeInternational Business Machines Corporation

InventorsHoichi Cheong, Hung Qui Le, John Stephen Muhich, Steven Wayne White

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Abstract

A method and apparatus for maintaining content of registers of a processor which uses the registers for processing instructions. Entries are stored in a buffer for restoring register content in response to an interruption by an interruptible instruction. Entries include information for reducing the number of entries selected for the restoring. A set of the buffer entries is selected, in response to the interruption and the information, for restoring register content. The set includes only entries which are necessary for restoring the content in response to the interruption so that the content of the processor registers may be restored in a single processor cycle, even if multiple entries are stored for a first one of the registers and multiple entries are stored for a second one of the registers.

Claims14

Dependent claims

A method for writing results to architected registers from processing of instructions, and restoring results to the architected registers in response to interruption of such an instruction, the method comprising the steps of:

a) successively dispatching instructions in a predetermined sequence for processing in a processor, including interruptible instructions and instructions targeting architected registers;
b) processing the instructions by at least one functional unit, including writing speculative results to the architected registers targeted by the instructions, wherein results i) for the architected registers, and ii) associated with a given one of the instructions, define a processor state for the given instruction;
c) storing the speculative results, as entries, in a history buffer;
d) restoring selected ones of the entries to the architected registers, in response to an interruption of one of the interruptible instructions, so that the architected registers are concurrently restored to such a processor state for the interrupted instruction, wherein for each architected register, only a single entry is selected for the restoring to the architected register, even if multiple entries are stored in the history buffer for the single architected register.

1 more element

An apparatus, for writing results to architected registers from processing of instructions, and restoring results to the architected registers in response to interruption of such an instruction, the apparatus comprising:

a) means for successively dispatching instructions in a predetermined sequence for processing in a processor, including instructions targeting architected registers and interruptible instructions;
b) means for processing the instructions by at least one functional unit, including writing speculative results to the architected registers targeted by the instructions, wherein results i) for the architected registers, and ii) associated with a given one of the instructions, define a processor state for the given instruction;
c) means for storing copies of the speculative results, as entries in a history buffer;
and
d) means for restoring selected ones of the entries to the architected registers, in response to an interruption of one of the interruptible instructions, so that the architected registers are concurrently restored to such a processor state for the interrupted instruction, wherein the means for restoring selected ones of the entries to the architected registers includes means for selecting only a single entry for any one of the architected registers, regardless of whether multiple entries are stored in the history buffer for the one architected register.

2 more elements

Dependencies are inferred from the claim text.