System for assigning boot strap processor in symmetric multiprocessor computer with watchdog reassignment

#Multiprocessor computers implement varying levels of symmetry. Master-slave processor computer systems are very asymmetric, whereas in computers designed with higher levels of symmetry, each of the working processors are capable of performing the same functions. In symmetric computers, the working processors share buses, address the same memory and basic input/output system (BIOS) resources, and receive the same array of interrupts.

#Symmetric multiprocessor computers also tend to have a non-hierarchal bus arbitration process. The Intel.RTM. Pentium-Pro.RTM. Processor Bus arbitration protocol, for example, supports fair arbitration between a maximum of four working processors in the typical multiprocessor configuration. A unique identification, i.e., agent ID of 0, 1, 2, or 3, is assigned to each working processor as part of the power-on configuration by a central agent that is also responsible for bus arbitration control. Bus arbitration between the working processors is then made using a round-robin algorithm, which arranges the working processors in a circular order of priority: 0, 1, 2, 3, 0, 1, 2, etc. The working processor with the highest priority becomes the bus owner on every arbitration event, and the working processor that owns the bus is allowed to request its use. Input/output and possibly memory subsystems may, however, have higher priority, defeating the immediate use of the bus by the working processor.

#The symmetry in some multiprocessor computers tends to break down when considering reset protocol in which the computer is bootstrapped after being powered-on or rebooted after an operating system failure. Pentium-Pro.RTM. multiprocessor systems fall into this class. The same working processor (called the boot strap processor) performs the bootstrapping operations every time the computer is powered-on. The bootstrapping can generally not be assigned among the other working processors even though they have access to the same computer system resources and would thus be capable of performing the role of boot strap processor.

#In the accompanying drawings, reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale; emphasis has instead been placed upon illustrating the principles of the invention. Of the drawings:

#FIG. 1 is a block diagram showing the prior art method for distributing arbitration phase bus request signals among the four processors of a multiprocessor computer;

#FIG. 2 is a block diagram showing a circuit for controlling the boot strap processor assignment process; and

#FIG. 1 shows the prior art bus arbitration aspects of a Pentium-Pro.RTM. multiprocessor computer having four working processors P0, P1, P2, P3.

#Each of the working processors includes four bus request pins BR0, BR1, BR2, BR3 that are associated with bus arbitration. The BR0 bus request pin is an input/output pin on each of the working processors and is used to signal arbitration requests for the bus during normal operation. The BR1, BR2, BR3 bus request pin of each working processor are input only pins, being used to monitor the arbitration requests of the respective other working processors.

#Bus request lines BREQ0#, BREQ1#, BREQ2#, BREQ3# are distributed among the four working processors P0, P1, P2, P3 in a rotating fashion. The BR0 pin of the first processor P0, for example is connected to the bus request line BREQ0#; the BR0 pin of the second processor P1 is connected to the BREQ1# bus request line, and so on. In a similar vein, the BR1 pin of the first processor P0 is connected to the BREQ1# bus request line; the BR1 pin of the second processor P1 is connected to the BREQ2# bus request line. The remaining lines and pins are connected in this fashion.