Hierarchical microcode implementation of floating point instructions for a microprocessor

A method for executing floating point instructions comprising;

• receiving a floating point instruction;
• generating a microcode entry point for said floating point instruction, wherein said microcode entry point identifies a microcode sequence that includes a floating point operation and one or more integer operations, wherein a floating point operand is larger than an integer operand, and multiple integer operations are required to load said floating point operand;
• conveying said floating point operation to a floating point instruction unit,
• dispatching said one or more integer operations into an instruction processing pipeline;
• executing said floating point operation;
• and
• storing a result of said floating point operation.

A microprocessor comprising:

• an instruction cache;
• an instruction alignment unit coupled to said instruction cache;
• a decode unit coupled to said instruction alignment unit;
• a functional unit coupled to said decode unit;
• a microcode unit that is configured to store a plurality of microcode sequences to effectuate the function of said floating point instructions, wherein one of said microcode sequences includes a floating point operation and one or more integer operations, wherein said integer operations load a floating point operand for said floating point operations;
• a floating point unit coupled to said microcode unit, wherein said microcode unit is configured to convey said floating point operation to said floating point unit, and
• said floating point unit is configured to execute said floating point operation when said integer operations have loaded said floating point operand;
• wherein said floating operand is larger then an integer operand, and multiple integer operations are required to load said floating point operand.