Parallel and scalable method for identifying valid instructions and a superscalar microprocessor including an instruction scanning unit employing the method

A superscalar microprocessor comprising:

• an instruction cache configured to store a plurality of bytes, corresponding start byte information identifying which ones of said plurality of bytes form a start byte of an instruction, and corresponding end byte information identifying which ones of said plurality of bytes form an end byte of an instruction, wherein said instruction cache includes an instruction scanning unit which, upon fetch of said plurality of bytes, is configured to scan said end byte information to create a plurality of masks indicative of potential instructions beginning at a respective one of said plurality of bytes and ending at a subsequent byte within said plurality of bytes, said subsequent byte identified by said end byte information as an end byte of an instruction, and wherein said instruction scanning unit is further configured to scan said start byte information in parallel with scanning said end byte information, and wherein said instruction scanning unit is configured to select certain ones of said plurality of masks corresponding to respective ones of said plurality of bytes which are identified by said start byte information as a start byte of said instruction;
• and
• an instruction alignment unit coupled to receive said plurality of bytes and said certain ones of said plurality of masks, wherein said instruction alignment unit is configured to route particular ones of said plurality of bytes to one of a plurality of decode units in accordance with one of said certain ones of said plurality of masks.

A method for identifying an instruction within a plurality of contiguous bytes, said instruction having a first boundary and a second boundary, said first boundary comprising a first one of said plurality of contiguous bytes and said second boundary comprising a second one of said plurality of contiguous bytes, said method comprising:

• identifying said first boundary of said instruction using a first set of boundary-identifying indications, wherein said first set of boundary-identifying indications includes a first plurality of indications, and wherein each of said first plurality of indications corresponds to one of said plurality of contiguous bytes and indicates if said one of said plurality of contiguous bytes forms said first boundary;
• creating a first mask identifying a first potential instruction having said first boundary and a third boundary;
• creating a second mask identifying a second potential instruction having said first boundary and a fourth boundary different from said third boundary;
• selecting said first mask as a selected mask if a second set of boundary-identifying indications indicates that said third boundary is said second boundary of said instruction, wherein said second set of boundary-identifying indications includes a second plurality of indications, and wherein each of said second plurality of indications corresponds to one of said plurality of contiguous bytes and indicates if said one of said plurality of contiguous bytes forms said second boundary;
• and
• selecting said second mask as said selected mask if said second set of boundary-identifying indications indicates that said fourth boundary is said second boundary of said instruction;
• whereby said selected mask identifies bytes within said plurality of contiguous bytes which form said instruction.

A superscalar microprocessor comprising:

• an instruction cache configured to store a plurality of bytes, corresponding first boundary information identifying which ones of said plurality of bytes form a first boundary of an instruction, and corresponding second boundary information identifying which ones of said plurality of bytes form a second boundary of an instruction, said instruction comprising bytes between a first one of said plurality of bytes indicated by said first boundary information and a second one of said plurality of bytes indicated by said second boundary information inclusive of said first one of said plurality of bytes and said second one of said plurality of bytes, wherein said instruction cache includes an instruction scanning unit which, upon fetch of said plurality of bytes, is configured to scan said first boundary information to create a plurality of masks indicative of potential instructions having a second boundary at a respective one of said plurality of bytes and a first boundary as indicated by said first boundary information, and wherein said instruction scanning unit is further configured to scan said second boundary information in parallel with scanning said first boundary information, and wherein said instruction scanning unit is configured to select certain ones of said plurality of masks corresponding to respective ones of said plurality of bytes which are identified by said second boundary information as a second boundary of said instruction;
• and
• an instruction alignment unit coupled to receive said plurality of bytes and said certain ones of said plurality of masks, wherein said instruction alignment unit is configured to route particular ones of said plurality of bytes to one of a plurality of decode units in accordance with one of said certain ones of said plurality of masks.